Chapter 4. Peripheral Hardware
4.1.4.1 Control of B.I.T
¡ È ¡ È
If bit3(BTCL) of CKCTLR is set to
1
, B.I.T is cleared, and then, after one machine
¡ È ¡ È
¡ È ¡ È
0 in reset
cycle, BTCL becomes
state.
0
, and B.I.T starts counting. BTCL is set to
Clock Control Register
7
0
-
-
WDTON
ENPCK
BTCL
BTS2
BTS1
BTS0
CKCTLR
W <00C7H>
BTCL
B.I.T Operation
0
1
free-run
Automatically cleared, after one cycle
4.1.4.2 Input Clock Selection of Basic Interval Timer
The input clock of B.I.T can be selected from the prescaler within a range of 2us to
256us by clock input selection bits(BTS2~BTS0). (at fex = 4MHz).
In reset state, or power on reset, BTS2=1, BTS1=1, BTS0=1 to secure the longest
oscillation stabilization time.
B.I.T can generate the wide range of basic interval time interrupt request(IFBIT) by
selecting prescaler output.
Interrupt interval can be selected to 8 kinds of interval time as shown in Table. 4.1.
4 - 5
HYNIX [ HYNIX SEMICONDUCTOR ]
