Chapter 4. Peripheral Hardware
By assigning bit6(WDTCL) of WDTR, 6-bit counter can be cleared
Watch Dog Timer Register
7
0
-
WDTCL
WDTR5
WDTR4
WDTR3
WDTR2
WDTR1
WDTR0
WDTR
W <00C8H>
Determine Interval of IFWDT
¡ ¿
Interval of IFWDT = Value of WDTR
Interval of IFBIT
WDTCL
Watch Dog Timer Operation
0
1
Free-run
Automatically cleared, after one machine cycle
(Caution) : after WDTCL = 1, timer maximum error is one cycle of IFBIT.
4.1.5.2 WDT Interrupt Interval
WDT Interrupt(IFWDT) interval is determined by the interrupt IFBIT interval of Basic
Interval Timer and the value of WDT Register.
Interval of IFWDT = (IFBIT interval) * (WDTR value)
¡ ¿
Interval of IFWDT : 512us
: 65,536us
1 = 512us (MIN>)
¡ ¿
63 = 4,128,768us (MAX>)
As IFBIT (Basic Interval Timer Interrupt Request) is used for input clock of WDT, Input
clock cycle is possible from 512us to 65,536us by BTS. (at fex = 4MHz)
*At Hardware reset time ,WDT starts automatically.Therefore, the user must select
the CKCTLR,WDTR before WDT overflow.
( Reset WDTR value = 0Fh,15
¡ ¿
interval of WDT = 65,536
15 = 983040 uS (about 1second ) )
4 - 8
HYNIX [ HYNIX SEMICONDUCTOR ]
