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GMM27333230ANTG-7K 参数 Datasheet PDF下载

GMM27333230ANTG-7K图片预览
型号: GMM27333230ANTG-7K
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM Module, 32MX72, 6ns, CMOS, DIMM-168]
分类和应用: 时钟动态存储器内存集成电路
文件页数/大小: 14 页 / 217 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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GMM27333230ANTG  
AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V)  
(Continued)  
- 8  
- 7K  
- 7J  
- 10K  
Parameter  
Symbol  
Unit Notes  
Min Max Min Max Min Max Min Max  
Write recovery or data-in  
to precharge lead time  
Active (a) to Active (b)  
command period  
8
-
-
10  
20  
-
-
10  
20  
-
-
15  
20  
-
-
ns  
ns  
1
1
t
RWL  
16  
t
RRD  
Refresh period  
-
64  
-
-
64  
-
-
64  
-
-
64  
-
ms  
us  
t
REF  
PLL Stabilization time  
200  
200  
200  
200  
6
t
STAB  
Notes :  
1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.40V.  
If tT is longer than 1ns,transition time compensation should be considered.  
2. Access time is measured at 1.40V. Load condition is CL = 50pF without termination.  
3. tLZ (min)defines the time at which the outputs achieves the low impedance state.  
4. tHZ (max)defines the time at which the outputs achieves the high impedance state.  
5. tCES define CKE setup time to CKE rising edge except Power down exit command.  
6. The on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB) before any  
operation can be guaranteed.  
Test Condition  
Input and output-timing reference levels: 1.4V  
Input waveform and output load: See following figures  
I/O  
2.4V  
OPEN  
80%  
20%  
input  
0.4V  
CL  
t
T
t
T
Rev. 1.1/Dec.99  
9