SDRAM Memory Module EEPROM Data Information
GMM27333230ATG-7J
00.05.09
Byte
Function described
Function support
HEX Code DEC Code BIN Code
Note
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64
65-71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Define # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM...) from appendix A
# Row addresses on this assembly
# Column addresses on this assembly
# Module banks on this assembly
128 Bytes
256 Bytes
SDRAM
12
11
1
72 bit
N/A
LVTTL
10.0 ns
6.0 ns
ECC
80
08
04
0C
0B
01
48
00
01
A0
60
02
80
04
04
01
8F
04
06
01
01
16
0F
F0
80
00
00
14
14
14
32
40
20
10
20
10
00
12
C8
E0
00
52
47
4D
4D
32
37
33
33
33
32
33
30
41
54
47
2D
37
4A
20
00
00
14
00
00
00
64
8D
00
00
00
00
00
00
00
00
00
00
00
128
008
004
012
011
001
072
000
001
160
096
002
128
004
004
001
143
004
006
001
001
022
015
240
128
000
000
020
020
020
050
064
032
016
032
016
000
018
200
224
000
082
071
077
077
050
055
051
051
051
050
051
048
065
084
071
045
055
074
32
10000000
00001000
00000100
00001100
00001011
00000001
01001000
00000000
00000001
10100000
01100000
00000010
10000000
00000100
00000100
00000001
10001111
00000100
00000110
00000001
00000001
00010110
00001111
11110000
10000000
00000000
00000000
00010100
00010100
00010100
00110010
01000000
00100000
00010000
00100000
00010000
00000000
00010010
11001000
Data width of this assembly...
...Data width continuation
Voltage interface standard of this assembly
SDRAM cycletime
SDRAM access from clock
DIMM configuration type (Non-parity, Parity, ECC)
Refresh rate/type
Normal(15.625us)
DRAM/SDRAM width, primary DRAM/SDRAM
Error checking SDRAM data width
Minimum clock delay, back to back random column address(tCCD)
Burst lengths supported
x4
x4
1 ns
Full Page Supported
# Banks on each SDRAM device
4 banks
2&3
0
CAS # latency
CS # latency
Write latency
SDRAM module attributes
0
Register(w/ PLL)
Support All(VCC:10%)
15.0 ns
SDRAM device attributes : General
Minimum clock cycle time at CL X-1
Maximum data access time from clock at CL X-1
Minimum clock cycle time at CL X-2
Maximum data access time from clock at CL X-2
Minimum row precharge time(tRP)
Minimum row active to row active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
Minimum RAS pulse width(tRAS)
Module bank density
Command and address signal input setup time(tAS)
Command and address signal input hold time(tAH)
Data signal input setup time(tDS)
Data signal input hold time(tDH)
Superset information (may be used in future)
SPD revision
8.0 ns
N/A
N/A
20 ns
20 ns
20 ns
50 ns
256 MBytes
2.0 ns
1.0 ns
2.0 ns
1.0 ns
TBD
Rev 1.2
Checksum for bytes 0-62
Manufacturers JEDEC ID code per JEP-106F
….. Continuation Manufacturers JEDEC ID Code
Manufacturing location
HME
11100000 1st Group
00000000
01010010 82d(free)
Korea
GMM27333230ATG-7J
Manufacturer's part number
=== Allowed characters include 0-9, A-Z and 'space' ===
01000111
01001101
01001101
00110010
00110111
00110011
00110011
00110011
00110010
00110011
00110000
01000001
01010100
01000111
00101101
00110111
01001010
00100000
00000000
00000000
00010100
00000000
00000000 98byte start
00000000
01100100
10001101
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
G
M
M
2
7
3
3
3
2
3
0
A
T
G
-
7
J
blank
Revision Code
Revision Code
Date Code
Rev 0
000
000
020
000
000
000
100
141
000
000
000
000
000
000
000
000
000
000
000
WW
20 ww
0 year
94
YY
Binary incremental
N/A
95-98
99-125
126
127
128-135
136-150
151-152
153-165
166
167-189
190-221
222
223-253
254
255
Assembly serial number
Manufacturer specific data
Intel specification for frequency
Intel specfication details for 100Mhz Support
System integrator's ID
CK0_CL3
System integrator's P/N
System integrator's D/C
System integrator's S/N
Checksum for bytes 128-165
Top level system serial no.
Open
Checksum for bytes 167-221
Open
Checksum for Bytes 223-253
Checksum for bytes 0-128
Source : Intel Rev. 1.2B
HYNIX [ HYNIX SEMICONDUCTOR ]
