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GMM27333230ANTG-7K 参数 Datasheet PDF下载

GMM27333230ANTG-7K图片预览
型号: GMM27333230ANTG-7K
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM Module, 32MX72, 6ns, CMOS, DIMM-168]
分类和应用: 时钟动态存储器内存集成电路
文件页数/大小: 14 页 / 217 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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GMM27333230ANTG  
Absolute Maximum Ratings  
Parameter  
Symbol  
VT  
Value  
Unit  
V
Note  
-0.5 to Vcc+0.5  
(<= 4.6 (max))  
Voltage on any pin relative to VSS  
Supply voltage relative to VSS  
Short circuit output current  
Power dissipation  
1
1
VCC  
IOUT  
PT  
-0.5 to +4.6  
50  
V
mA  
W
C
1.0  
Operating temperature  
Topr  
Tstg  
0 to +70  
-55 to +125  
Storage temperature  
C
Notes : 1. Respect to VSS  
Recommended DC Operating Conditions (Ta = 0 to + 70C)  
Parameter  
Symbol  
VCC, VCCQ  
VSS, VSSQ  
VIH  
Min  
3.0  
0
Max  
3.6  
Unit  
V
Note  
1
Supply voltage  
0
V
Input high voltage  
Input low voltage  
2.0  
-0.3  
Vcc + 0.3  
0.8  
V
1, 2  
1,3  
VIL  
V
Notes : 1. All voltage referred to VSS.  
2. VIH (max) = 5.6V for pulse width <= 3ns  
3. VIL (min) = -2.0V for pulse width <= 3ns  
Registered DIMM Operation  
1. All control and address signals are registered on-DIMM register and hence delayed by one cycle in  
arriving at the SDRAMs. But data is not registered in the register.  
2. CAS latency defines the delay from when a READ command is registered on a rising clock edge to  
when the data from that READ command becomes available at the outputs. Do not confuse DIMM  
CAS latency with the SDRAM CAS latency which is one clock less.  
Rev. 1.1/Dec.99  
5