GMM27333230ANTG
Pin Description
Pin Name
DESCRIPTION
CK0, 1, 2, 3
(input pins)
CK is the master clock input to this pin. The other input signals are
referred at CK rising edge.
This pin determines whether or not the next CK is valid. If CKE is
High, the next CK rising edge is valid. If CKE is Low, the next CK
rising edge is invalid. This pin is used for power-down and clock
suspend modes.
CKE0,1
(input pin)
When S is Low, the command input cycle becomes valid. When S is
high, all inputs are ignored. However, internal operations (bank active,
burst operations, etc.) are held.
S0,1,2,3
(input pins)
Although these pin names are the same as those of conventional
DRAMs, they function in a different way. These pins define operation
commands (read, write, etc.) depending on the combination of their
voltage levels. For details, refer to the command operation section.
RAS, CAS and WE
(input pins)
Row address (AX0 to AX11) is determined by A0 to A11 level at the
bank active command cycle CK rising edge. Column address is
determined by A0 to A9 level at the read or write command cycle CK
rising edge. And this column address becomes burst access start
address. A10 defines the precharge mode. When A10 = High at the
precharge command cycle, both banks are precharged. But when A10 =
Low at the precharge command cycle, only the bank that is selected by
BA0 is precharged.
A0 ~ A11
(input pins)
BA0,1 are bank select signal. If BA0 is Low and BA1 is High, bank 0 is
selected. If BA0 is High and BA1 is Low, bank 1 is selected. If BA0 is
Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is
High, bank 3 is selected.
BA0,1
(input pin)
DQ0 ~ DQ63
CB0 ~ CB7
(I/O pins)
Data is input and output from these pins. These pins are the same as
those of a conventional DRAMs. Data is not latched in the register.
DQMB controls input/output buffers.
-Read operation: If DQMB is High, The output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
-Write operation: If DQMB is High, the previous data is held (the new data
is not written). If DQMB is Low, the data is written.
DQMB0 ~ DQMB7
(input pins)
VCC
3.3 V is applied. (VCC is for the internal circuit)
(power supply pins)
VSS
Ground is connected. (VSS is for the internal circuit)
(power supply pins)
If REGE input is high, permits the DIMM to operate in `registered mode`.
If REGE input is low, permits the DIMM to operate in `buffered mode`.
REGE
NC
No Connection pins.
Rev. 1.1/Dec.99
4
HYNIX [ HYNIX SEMICONDUCTOR ]
