HI-3110
GENERAL PURPOSE PINS ENABLE REGISTER: GPINE
GPINE7:4
GPINE3:0
(Write, SPI Op-code 0x22)
(Read, SPI Op-code 0xE8)
7
6
5
4
3
2
1
0
LSB
MSB
Setting bits in the General Purpose Pins Enable Register allows the user to reflect the values of the Interrupt Flag bits in the INTF
Register or the Status Flag bits in the STATF Register on the GP1 andGP2 pins.
Bit Name
R/W Default Description
7-4 GPINE7:43:0 R/W
0000 Reflect status of interrupt flag bits in INTF or status flag bits in STATF on GP2 pin as follows:
0000: GP2 pin is asserted when F0MESS bit is set in register INTF.
0001: GP2 pin is asserted when F1MESS bit is set in register INTF.
0010: GP2 pin is asserted when WAKEUPbit is set in register INTF.
0011: GP2 pin is asserted when MCHG bit is set in register INTF.
0100: GP2 pin is asserted when BUSERR bit is set in register INTF.
0101: GP2 pin is asserted whenTXCPLTbit is set in register INTF.
0110: GP2 pin is asserted when RXFIFO bit is set in register INTF.
0111: GP2 pin is asserted when RXTMPbit is set in register INTF.
1000: GP2 pin is asserted when RXFFULLbit is set in register STATF.
1001: GP2 pin is asserted when RXFMPTYbit is set in register STATF.
1010: GP2 pin is asserted when BUSOFF bit is set in register STATF.
1011: GP2 pin is asserted when ERRPbit is set in register STATF.
1100: GP2 pin is asserted when ERRW bit is set in register STATF.
1101: GP2 pin is asserted whenTXHISF bit is set in register STATF.
1110: GP2 pin is asserted whenTXFULLbit is set in register STATF.
1111: GP2 pin is asserted whenTXMPTYbit is set in register STATF.
3-0 GPINE3:0
R/W
0000 Reflect status of interrupt flag bits in INTF or status flag bits in STATF on GP1 pin as follow:
0000: GP1 pin is asserted when F0MESS bit is set in register INTF.
0001: GP1 pin is asserted when F1MESS bit is set in register INTF.
0010: GP1 pin is asserted when WAKEUPbit is set in register INTF.
0011: GP1 pin is asserted when MCHG bit is set in register INTF.
0100: GP1 pin is asserted when BUSERR bit is set in register INTF.
0101: GP1 pin is asserted whenTXCPLTbit is set in register INTF.
0110: GP1 pin is asserted when RXFIFO bit is set in register INTF.
0111: GP1 pin is asserted when RXTMPbit is set in register INTF.
1000: GP1 pin is asserted when RXFFULLbit is set in register STATF.
1001: GP1 pin is asserted when RXFMPTYbit is set in register STATF.
1010: GP1 pin is asserted when BUSOFF bit is set in register STATF.
1011: GP1 pin is asserted when ERRPbit is set in register STATF.
1100: GP1 pin is asserted when ERRW bit is set in register STATF.
1101: GP1 pin is asserted whenTXHISF bit is set in register STATF.
1110: GP1 pin is asserted whenTXFULLbit is set in register STATF.
1111: GP1 pin is asserted whenTXMPTYbit is set in register STATF.
HOLT INTEGRATED CIRCUITS
28
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
