HI-3110
STATUS FLAG ENABLE REGISTER: STATE
TXFU
T
L
X
LF
H
E
ISFFE
RXFMRTXYFFFEULLFE
(Write, SPI Po-code 0x1E)
(Read, SPI Op-code 0xE6)
7
6
5
4
3
2
1
0
LSB
MSB
Setting bits in the Status Flag Enable Register causes the STAT pin to go high when any of the corresponding bits in the Status Flag
Register are set by HI-3110 as a result of the related events described below.
Bit Name
TXMTYFE
R/W Default Description
7
6
5
4
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
1
Transmit FIFO empty status flag enable.
Setting this bit causes the status of theTXMTYbit in the Status Flag Register to be output on
the STATpin.
TXFULLFE
TXHISFFE
ERRWFE
Transmit FIFO full status flag enable.
Setting this bit causes the status of theTXFULLbit in the Status Flag Register to be output on
the STATpin.
Transmit History FIFO full status flag enable.
Setting this bit causes the status of theTXHISF bit in the Status Flag Register to be output on
the STATpin.
Error warning status flag enable (96 £ (TEC or REC) £ 127).
Setting this bit causes the status of the ERRW bit in the Status Flag Register to be output on the
STATpin.
ERRPFE
Error Passive status flag enable.
Setting this bit causes the status of the ERRPbit in the Status Flag Register to be output on the
STATpin.
BUSOFFFE
RXFMTYFE
Bus-off status flag enable.
Setting this bit causes the status of the BUSOFF bit in the Status Flag Register to be output on
the STATpin.
Receive FIFO empty status flag enable.
Setting this bit causes the status of the RXFMTYbit in the Status Flag Register to be
output on the STATpin.
0
RXFFULLFE R/W
0
Receive FIFO full status flag enable.
Setting this bit causes the status of the RXFFULLbit in the Status Flag Register to be output on
the STATpin.
HOLT INTEGRATED CIRCUITS
27
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
