HI-3110
INTERRUPT ENABLE REGISTER: INTE
TIE
RXFIF
T
O
X
I
C
E
PL
F1MEFS0SMIEESIE
(Write SPI Op-code 0x1C)
(Read, SPI Op-code 0xE4)
7
6
5
4
3
2
1
0
LSB
MSB
Setting bits in the Interrupt Enable Register causes a hardware interrupt to be generated at the INT pin when the
corresponding bits in the Interrupt Flag Register are set by HI-3110 as a result of the related events described below.
Bit Name
R/W Default Description
7
RXTMPIE
R/W
0
Enable interrupt when a message is received in the temporary receive buffer (unfiltered).
Setting this bit causes a hardware interrupt to be generated at the INTpin when the RXTMPbit
is set in the INTF register.
6
RXFIFOIE
R/W
0
Enable interrupt when a message is received in the receive FIFO (filtered).
Setting this bit causes a hardware interrupt to be generated at the INTpin when the
RXFIFO bit is set in the INTF register.
5
4
3
2
1
TXCPLTIE
BUSERRIE
MCHGIE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Enable interrupt when a successful transmission is complete.
Setting this bit causes a hardware interrupt to be generated at the INTpin when theTXCPLTbit
is set in the INTF register.
Enable interrupt when a bus error occurs.
Setting this bit causes a hardware interrupt to be generated at the INT pin when the BUSERR
bit is set in the INTF register.
Enable interrupt when a mode change occurs.
Setting this bit causes a hardware interrupt to be generated at the INTpin when the MCHG bit
is set in the INTF register.
WAKEUPIE
F1MESSIE
Enable interrupt when HI-3110 wakes up from Sleep Mode.
Setting this bit causes a hardware interrupt to be generated at the INTpin when the WAKEUP
bit is set in the INTF register.
Enable interrupt when filter one passes a message.
Setting this bit causes a hardware interrupt to be generated at the INTpin when the F1MESS
bit is set in the INTF register.
0
F0MESSIE
R/W
0
Enable interrupt when filter zero passes a message.
Setting this bit causes a hardware interrupt to be generated at the INTpin when the F0MESS
bit is set in the INTF register.
HOLT INTEGRATED CIRCUITS
25
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
