欢迎访问ic37.com |
会员登录 免费注册
发布采购

HI-3111PCMF 参数 Datasheet PDF下载

HI-3111PCMF图片预览
型号: HI-3111PCMF
PDF下载: 下载PDF文件 查看货源
内容描述: 航空电子与CAN收发器集成控制器 [Avionics CAN Controller with Integrated Transceiver]
分类和应用: 电子控制器航空
文件页数/大小: 53 页 / 178 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
 浏览型号HI-3111PCMF的Datasheet PDF文件第26页浏览型号HI-3111PCMF的Datasheet PDF文件第27页浏览型号HI-3111PCMF的Datasheet PDF文件第28页浏览型号HI-3111PCMF的Datasheet PDF文件第29页浏览型号HI-3111PCMF的Datasheet PDF文件第31页浏览型号HI-3111PCMF的Datasheet PDF文件第32页浏览型号HI-3111PCMF的Datasheet PDF文件第33页浏览型号HI-3111PCMF的Datasheet PDF文件第34页  
HI-3110  
SERIAL PERIPHERAL INTERFACE  
SERIALPERIPHERALINTERFACE (SPI) BASICS  
edges on SCK latch input data into the master and slave  
devices, starting with each byte’s most-significant bit. The  
HI-3110 SPI can be clocked at 20 MHz.  
The HI-3110 uses an SPI synchronous serial interface for  
host access to internal registers and data FIFOs. Host  
serial communication is enabled through the Chip Select  
(CS) pin, and is accessed via a three-wire interface  
consisting of Serial Data Input (SI) from the host, Serial  
Data Output (SO) to the host and Serial Clock (SCK). All  
read / write cycles are completely self-timed.  
Multiple bytes may be transferred when the host holds CS  
low after the first byte transferred, and continues to clock  
SCK in multiples of 8 clocks. A rising edge on CS chip  
select terminates the serial transfer and reinitializes the  
HI-3110 SPI for the next transfer. If CS goes high before a  
full byte is clocked by SCK, the incomplete byte clocked  
into the device SI pin is discarded.  
The SPI (Serial Peripheral Interface) protocol specifies  
master and slave operation; the HI-3110 operates as an  
SPI slave.  
In the general case, both master and slave simultaneously  
send and receive serial data (full duplex), per Figure 9  
below. However the HI-3110 operates half duplex,  
maintaining high impedance on the SO output, except  
when actually transmitting serial data. When the HI-3110  
is sending data on SO during read operations, activity on  
its SI input is ignored. Figures 10 and 11 show actual  
behavior for the HI-3110 SO output.  
The SPI protocol defines two parameters, CPOL (clock  
polarity) and CPHA (clock phase). The possible CPOL-  
CPHA combinations define four possible "SPI Modes".  
Without describing details of the SPI modes, the HI-3110  
operates in mode 0 where input data for each device  
(master and slave) is clocked on the rising edge of SCK,  
and output data for each device changes on the falling  
edge (CPHA = 0, CPOL = 0). Be sure to set the host SPI  
logic for mode 0.  
As seen in Figure 9, SPI Mode 0 holds SCK in the low state  
when idle. The SPI protocol transfers serial data as 8-bit  
bytes. Once CS chip select is asserted, the next 8 rising  
0
1
2
3
4
5
6
7
SCK (SPI Mode 0)  
SI  
MSB  
LSB  
LSB  
High Z  
High Z  
SO  
MSB  
CS  
Figure 9. Generalized Single-Byte Transfer Using SPI Protocol Mode 0  
HOLT INTEGRATED CIRCUITS  
30  
 复制成功!