HI-3110
STATUS FLAG REGISTER: STATF
TXFU
T
L
XL
HISF
RXFMRTXYFFULL
(Read-only)
(Read, SPI Op-code 0xE2)
7
6
5
4
3
2
1
0
LSB
MSB
The Status Flag Register STATF bits will be set by HI-3110 when the corresponding related events described below occur. Unlike the
Interrupt Flag Register, reading this register will NOT clear all bits. These bits are reset automatically by HI-3110 when the described
status for each bit changes (e.g. if TXMTY is set and a message is loaded to the transmit FIFO, TXMTY will be automatically cleared
by HI-3110). If individual bits in the Status Flag Enable Register STATFE are set, the STAT pin will pulse high when any of the enabled
STATF bits are set. The value of individual bits in the STATF register may also be reflected on the GP1 and GP2 pins by setting the
correct bit combinations in the General Purpose Pins Enable Register GPINE.
Bit Name
R/W Default Description
7
6
5
TXMTY
TXFULL
TXHISF
R
R
R
1
0
0
Transmit FIFO is empty.
This bit is set when the transmit FIFO is empty. This is the default following Reset.
Transmit FIFO is full.
This bit is set when the transmit FIFO is full.
Transmit history FIFO full.
This bit is set when the transmit history FIFO is full. Up to eight messages can be stored in the
transmit history FIFO (Note: a user generated message tag and a time tag are stored with each
message).
4
3
2
1
0
ERRW
R
R
R
R
R
0
0
0
1
0
Error warning flag.
This bit is set when 96 £ (TEC or REC) £ 127.
ERRP
Error passive indicator.
This bit is set when the device enters error passive mode.
BUSOFF
RXFMTY
RXFFULL
BUSOFF indicator.
This bit is set when the device enters bus-off state.
Receive FIFO empty.
This bit is set when the receive FIFO is empty. This is the default following Reset.
Receive FIFO full.
This bit is set when the receive FIFO is full.
HOLT INTEGRATED CIRCUITS
26
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
