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HI-3111PCMF 参数 Datasheet PDF下载

HI-3111PCMF图片预览
型号: HI-3111PCMF
PDF下载: 下载PDF文件 查看货源
内容描述: 航空电子与CAN收发器集成控制器 [Avionics CAN Controller with Integrated Transceiver]
分类和应用: 电子控制器航空
文件页数/大小: 53 页 / 178 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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HI-3110  
INTERRUPT FLAG REGISTER: INTF  
T
RXFIF  
T
O
XCPL  
F1MEFS0SMES  
(Read only)  
(Read, SPI Op-code 0xDE)  
7
6
5
4
3
2
1
0
LSB  
MSB  
The Interrupt Flag Register INTF bits will be set by HI-3110 when the corresponding related events described below occur. If  
individual bits in the Interrupt Enable Register INTE are set, the INT pin will be latched high when any of the corresponding INTF bits  
are set. This alerts the host that one of the conditions below has occurred. Reading this register will clear all bits and reset the INT pin.  
The value of individual bits in the INTF register may also be reflected on the GP1 and GP2 pins by setting the correct bit combinations  
in the General Purpose Pins Enable Register GPINE (see section General Purpose Pins Enable Register).  
Bit Name  
R/W Default Description  
7
RXTMP  
R
0
Message received in temporary receive buffer (unfiltered).  
This bit is set when a valid message is received in the temporary receive buffer.  
6
RXFIFO  
R
0
Message received in FIFO (filtered).  
This bit is set when a valid message passes the filter criteria and is passed from the  
temporary receive buffer to the receive FIFO.  
5
4
TXCPLT  
R
R
0
0
Successful transmission complete.  
This bit is set when a message is successfully transmitted.  
BUSERR  
Bus Error.  
This bit is set when a bus error occurs. Bits 4:0 in the ERR register can be read to determine  
the source of the error.  
3
MCHG  
R
0
Mode Change bit.  
This bit is set when the mode of operation is changed.Any pending transmissions in the  
transmit FIFO will be completed (FIFO will be emptied) before the mode change occurs.  
2
1
WAKEUP  
F1MESS  
R
R
0
0
Wake-Up detected.  
This bit is set when the HI-3110 wakes up from Sleep Mode in response to bus activity.  
Filter 1 passed a valid message.  
This bit is set when receive filter one passes a valid message. FILHIT3:0 bits will also be set to  
<1001> in the Message Status Register, MESSTAT.  
0
F0MESS  
R
0
Filter 0 passed a valid message.  
This bit is set when receive filter zero passes a valid message. FILHIT3:0 bits will also be set to  
<1000> in the Message Status Register, MESSTAT.  
HOLT INTEGRATED CIRCUITS  
24  
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