HT48R0AA-1
The states of the registers is summarized in the table.
Reset
(Power On)
WDT Time-out RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
Register
MP
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
Program
Counter
000H
000H
000H
000H
000H
TBLP
TBLH
WDTS
STATUS
INTC
TMR0
TMR0C
TMR1
TMR1C
PA
xxxx xxxx
-xxx xxxx
0000 0111
--00 xxxx
-000 0000
xxxx xxxx
00-0 1000
xxxx xxxx
00-0 1---
uuuu uuuu
-uuu uuuu
0000 0111
--1u uuuu
-000 0000
xxxx xxxx
00-0 1000
xxxx xxxx
00-0 1---
uuuu uuuu
-uuu uuuu
0000 0111
--uu uuuu
-000 0000
xxxx xxxx
00-0 1000
xxxx xxxx
00-0 1---
uuuu uuuu
-uuu uuuu
0000 0111
--01 uuuu
-000 0000
xxxx xxxx
00-0 1000
xxxx xxxx
00-0 1---
uuuu uuuu
-uuu uuuu
uuuu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uu-u uuuu
uuuu uuuu
uu-u u---
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
---- ---u
PAC
PB
PBC
PC
PCC
PD
PDC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Timer/Event Counter
TMR0/TMR1 location; writing to TMR0/TMR1 makes
the starting value be placed in the Timer/Event Counter
0/1 preload register and reading TMR0/TMR1 retrieves
the contents of the Timer/Event Counter 0/1. The
TMR0C/TMR1C is a timer/event counter control regis-
ter, which defines some configuration options.
Two timer/event counters (TMR0, TMR1) are imple-
mented in the microcontroller. The Timer/Event Counter
0 contains an 8-bit programmable count-up counter and
the clock may come from an external source or from the
system clock. The Timer/Event Counter 1 also contains
an 8-bit programmable count-up counter and the clock
may come from an external source or from the system
clock divided by 4.
The TMR0C is the Timer/Event Counter 0 control regis-
ter, which defines the operating mode, counting enable
or disable and active edge.
Using an external clock input allows the user to count ex-
ternal events, measure time internals or pulse widths, or
generate an accurate time base. While using the internal
clock allows the user to generate an accurate time base.
The T0M0, T0M1, T1M0, T1M1 bits define the operating
mode. The event count mode is used to count external
events, which means the clock source comes from an
external (TMR0/TMR1) pin. The timer mode functions
as a normal timer with the clock source coming from the
fINT clock/instruction clock (Timer0/Timer1). The pulse width
measurement mode can be used to count the high or low
level duration of the external signal (TMR0/TMR1). The
counting is based on the fINT clock/instruction clock
(Timer0/Timer1).
The Timer/Event Counter 0 can generate PFD signal by
using external or internal clock and the PFD frequency
is determine by the equation fINT/[2´(256-N)].
There are 2 registers related to the Timer/Event Counter
0/1; TMR0/TMR1 ([0DH]/[10H]), TMR0C/TMR1C
([0EH]/[11H]). Two physical registers are mapped to
Rev. 1.10
13
July 27, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
