HT48R0AA-1
Input/Output Ports
starts counting not according to the logic level but ac-
cording to the transient edges. In the case of counter
overflows, the counter 0/1 is reloaded from the
Timer/Event Counter 0/1 preload register and issues the
interrupt request just like the other two modes. To en-
able the counting operation, the timer ON bit
(T0ON/T1ON; bit 4 of TMR0C/TMR1C) should be set to
1. In the pulse width measurement mode, the
T0ON/T1ON will be cleared automatically after the mea-
surement cycle is completed. But in the other two
modes the T0ON/T1ON can only be reset by instruc-
tions. The overflow of the Timer/Event Counter 0/1 is
one of the wake-up sources. No matter what the opera-
tion mode is, writing a 0 to ET0I/ET1I can disable the
corresponding interrupt services.
There are 23 bidirectional input/output lines in the
microcontroller, labeled from PA to PD, which are mapped
to the data memory of [12H], [14H], [16H] and [18H] re-
spectively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2 ris-
ing edge of instruction ²MOV A,[m]² (m=12H, 14H, 16H or
18H). For output operation, all the data is latched and re-
mains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trig-
ger input with or without pull-high resistor structures can
be reconfigured dynamically under software control. To
function as an input, the corresponding latch of the con-
trol register must write a ²1². The input source also de-
pends on the control register. If the control register bit is
²1², the input will read the pad state. If the control regis-
ter bit is ²0², the contents of the latches will move to the
internal bus. The latter is possible in the
²read-modify-write² instruction.
In the case of Timer/Event Counter 0/1 OFF condition,
writing data to the Timer/Event Counter 0/1 preload
register will also reload that data to the Timer/Event
Counter 0/1. But if the Timer/Event Counter 0/1 is turned
on, data written to it will only be kept in the Timer/Event
Counter 0/1 preload register. The Timer/Event Counter
0/1 will still operate until overflow occurs (a Timer/Event
Counter 0/1 reloading will occur at the same time). When
the Timer/Event Counter 0/1 (reading TMR0/TMR1) is
read, the clock will be blocked to avoid errors. As clock
blocking may result in a counting error, this must be taken
into consideration by the programmer.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high con-
figuration options). Each bit of these input/output
latches can be set or cleared by ²SET [m].i² and ²CLR
[m].i² (m=12H, 14H, 16H or 18H) instructions.
The bit0~bit2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of the
Timer/Event Counter 0. The definitions are as shown.
The overflow signal of the Timer/Event Counter 0 can be
used to generate PFD signals for buzzer driving.
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Timer/Event Counter 1
Rev. 1.10
15
July 27, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
