HT48R0AA-1
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
The I/O functions of PB0/PB1 are shown below.
PB0 I/O
I
I
I
I
O
B
0
x
I
O
B
1
x
O
I
O
I
O
I
O
O
O
O
B
0
O
O
B
1
PB1 I/O
O
C
x
PB0/PB1 Mode
PB0 Data
x
x
x
I
C
D
x
B
0
x
0
I
B
1
x
B
I
C
D0
D1
D0
D1
Each line of port A has a capability of waking-up the de-
vice. The highest 2 bits of port C and the highest 7-bit of
port D are not physically implemented; on reading them a
²0² is returned whereas writing then results in
no-operation.
PB1 Data
D
I
x
x
PB0 Pad Status
PB1 Pad Status
I
I
D
I
0
B
B
I
D
0
B
0
Note:
²I² input, ²O² output, ²D, D0, D1² data,
There is a pull-high configuration option available for all
I/O lines (bit configuration option). Once the pull-high
configuration option of an I/O line is selected, the I/O line
have pull-high resistor. Otherwise, the pull-high resistor
is absent. It should be noted that a non-pull-high I/O line
operating in input mode will cause a floating state.
²B² buzzer configuration option, BZ or BZ, ²x²
don¢t care
²C² CMOS output
The external input pins TMR0 and TMR1 are pin-shared
with pin PC0 and PC5 respectively, and the external in-
terrupt pin INT is pin-shared with the I/O pin PD0.
The PB0 and PB1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ configuration option is se-
lected, the output signal in output mode of PB0/PB1 will
be the PFD signal generated by the Timer/Event Coun-
ter 0 overflow signal. The input mode always remain in
its original functions. Once the BZ/BZ configuration op-
tion is selected, the buzzer output signals are controlled
by the PB0 data register only.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
V
D
D
P
u
l
l
-
h
i
g
h
C
o
n
t
r
o
l
B
i
t
O
p
t
i
o
n
D
Q
D
a
t
a
B
u
s
W
r
i
t
e
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
C
K
Q
S
P
P
P
P
A
B
C
D
0
~
P
A
7
C
h
i
p
R
e
s
e
t
0
~
P
B
7
0
~
P
C
5
R
e
a
d
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
0
D
a
t
a
B
i
t
D
C
Q
W
r
i
t
e
D
a
t
a
R
e
g
i
s
t
e
r
K
Q
S
M
U
P
B
0
(
P
B
0
,
P
B
1
O
n
l
y
)
X
B
Z
/
B
Z
B
Z
E
N
M
(
P
B
0
,
P
B
1
o
n
l
y
)
U
X
R
e
a
d
D
a
t
a
R
e
g
i
s
t
e
r
S
y
s
t
e
m
W
a
k
e
-
u
p
O
P
0
~
O
P
7
(
P
A
o
n
l
y
)
T
M
R
0
f
o
r
P
C
0
o
n
l
y
T
M
R
1
f
o
r
P
C
5
o
n
l
y
I
N
T
f
o
r
P
D
0
o
n
l
y
Input/Output Ports
Rev. 1.10
16
July 27, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
