HT48R0AA-1
Bit No.
Label
EMI
EEI
Function
0
1
2
3
4
5
6
7
Controls the master (global) interrupt (1=enable; 0=disable)
Controls the external interrupt (1=enable; 0=disable)
Controls the Timer/Event Counter 0 interrupt (1=enable; 0= disable)
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
External interrupt request flag (1=active; 0=inactive)
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
Unused bit, read as ²0²
ET0I
ET1I
EIF
T0F
T1F
¾
INTC (0BH) Register
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
range from 24kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchro-
nize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of os-
cillation may vary with VDD, temperatures and the chip
itself due to process variations. It is, therefore, not suit-
able for timing sensitive operations where an accurate
oscillator frequency is desired.
Interrupt Source
External Interrupt
Priority Vector
1
2
3
04H
08H
0CH
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external compo-
nents are required. In stead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to get a
frequency reference, but two external capacitors in
OSC1 and OSC2 are required.
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Once the interrupt request flags (T0F, T1F, EIF) are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction. It is
recommended that a program does not use the ²CALL
subroutine² within the interrupt subroutine. Interrupts of-
ten occur in an unpredictable manner or need to be ser-
viced immediately in some applications. If only one stack
is left and enabling the interrupt is not well controlled, the
original control sequence will be damaged once the
²CALL² operates in the interrupt subroutine.
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
tem enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of 65ms at 5V. The WDT oscillator can be disabled by con-
figuration options to conserve power.
Watchdog Timer - WDT
Oscillator Configuration
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), determines the configuration
options. This timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by configuration options. If the
Watchdog Timer is disabled, all the executions related
to the WDT result in no operation.
There are 2 oscillator circuits in the microcontroller.
V
D
D
O
S
C
1
O
S
C
1
4
7
0
p
F
S
Y
S
O
S
C
2
O
S
C
2
N
M
O
S
O
p
e
n
D
r
a
i
n
C
r
y
s
t
a
l
O
s
c
i
l
l
a
t
o
r
R
C
O
s
c
i
l
l
a
t
o
r
Once the internal WDT oscillator (RC oscillator with a
period of 65ms at 5V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 17ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.1s at 5V
System Oscillator
All of them are designed for system clocks, namely the
external RC oscillator and the external Crystal oscillator,
which are determined by configuration options. No matter
what oscillator type is selected, the signal provides the
system clock. The HALT mode stops the system oscilla-
tor and ignores an external signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must
Rev. 1.10
10
July 27, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
