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HT48R0AA-1 参数 Datasheet PDF下载

HT48R0AA-1图片预览
型号: HT48R0AA-1
PDF下载: 下载PDF文件 查看货源
内容描述: 高性价比的I / O型8位OTP MCU [Cost-Effective I/O Type 8-Bit OTP MCU]
分类和应用:
文件页数/大小: 40 页 / 258 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT48R0AA-1  
·
Location 00CH  
Program Memory - ROM  
The program memory is used to store the program in-  
structions which are to be executed. It also contains  
data, table, and interrupt entries, and is organized into  
4096´15 bits, addressed by the program counter and ta-  
ble pointer.  
This location is reserved for the Timer/Event Counter  
1 interrupt service program. If a timer interrupt results  
from a Timer/Event Counter 1 overflow, and the inter-  
rupt is enabled and the stack is not full, the program  
begins execution at location 00CH.  
·
Certain locations in the program memory are reserved  
for special usage:  
Table location  
Any location in the ROM space can be used as  
look-up tables. The instructions ²TABRDC [m]² (the  
current page, one page=256 words) and ²TABRDL  
[m]² (the last page) transfer the contents of the  
lower-order byte to the specified data memory, and  
the higher-order byte to TBLH (08H). Only the desti-  
nation of the lower-order byte in the table is  
well-defined, the other bits of the table word are trans-  
ferred to the lower portion of TBLH, and the remaining  
1-bit words are read as ²0². The Table Higher-order  
byte register (TBLH) is read only. The table pointer  
(TBLP) is a read/write register (07H), which indicates  
the table location. Before accessing the table, the lo-  
cation must be placed in the TBLP. The TBLH is read  
only and cannot be restored. If the main routine and  
the ISR (Interrupt Service Routine) both employ the  
table read instruction, the contents of the TBLH in the  
main routine are likely to be changed by the table read  
instruction used in the ISR. Errors can occur. In other  
words, using the table read instruction in the main rou-  
tine and the ISR simultaneously should be avoided.  
However, if the table read instruction has to be applied  
in both the main routine and the ISR, the interrupt is  
supposed to be disabled prior to the table read in-  
struction. It will not be enabled until the TBLH has  
been backed up. All table related instructions require  
two cycles to complete the operation. These areas  
may function as normal program memory depending  
upon the requirements.  
·
Location 000H  
This area is reserved for program initialization. After a  
chip reset, the program always begins execution at lo-  
cation 000H.  
·
Location 004H  
This area is reserved for the external interrupt service  
program. If the INT input pin is activated, the interrupt  
is enabled and the stack is not full, the program begins  
execution at location 004H.  
·
Location 008H  
This area is reserved for the Timer/Event Counter 0 in-  
terrupt service program. If a timer interrupt results from a  
Timer/Event Counter 0 overflow, and if the interrupt is  
enabled and the stack is not full, the program begins ex-  
ecution at location 008H.  
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Stack Register - STACK  
This is a special part of the memory which is used to  
save the contents of the Program Counter only. The  
stack is organized into 4 levels and is neither part of the  
data nor part of the program space, and is neither read-  
able nor writeable. The activated level is indexed by the  
stack pointer (SP) and is neither readable nor writeable.  
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Program Memory  
Table Location  
Instruction  
*11  
P11  
1
*10  
P10  
1
*9  
P9  
1
*8  
P8  
1
*7  
*6  
*5  
*4  
*3  
*2  
*1  
*0  
TABRDC [m]  
TABRDL [m]  
@7  
@7  
@6  
@6  
@5  
@5  
@4  
@4  
@3  
@3  
@2  
@2  
@1  
@1  
@0  
@0  
Table Location  
P11~P8: Current program counter bits  
Note: *11~*0: Table location bits  
@7~@0: Table pointer bits  
Rev. 1.10  
7
July 27, 2007