HT48R0AA-1
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call or return
from subroutine, initial reset, internal interrupt, external
interrupt or return from interrupts, the PC manipulates
the program transfer by loading the address corre-
sponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme ensures that each in-
struction is effectively executed in a cycle. If an instruc-
tion changes the contents of the program counter, such
as subroutine calls or jumps, in which case, two cycles
are required to complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
S
y
s
t
e
m
C
l
o
c
k
O
S
C
2
(
R
C
o
n
l
y
)
P
C
P
C
+
1
P
C
+
2
P
C
F
e
t
c
h
I
N
S
T
(
P
C
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
-
1
)
F
e
t
c
h
I
N
S
T
(
P
C
+
1
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
)
F
e
t
c
h
I
N
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution Flow
Program Counter
Mode
*11
0
*10
0
*9
0
*8
0
*7
0
*6
0
*5
0
*4
0
*3
0
*2
0
*1
0
*0
0
Initial Reset
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Skip
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Program Counter+2
@7 @6 @5 @4 @3 @2 @1 @0
Loading PCL
*11
*10
*9
#9
S9
*8
#8
S8
Jump, Call Branch
#11 #10
S11 S10
#7
S7
#6
S6
#5
S5
#4
S4
#3
S3
#2
S2
#1
S1
#0
S0
Return from Subroutine
Program Counter
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
S11~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.10
6
July 27, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
