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HT48CA0-2 参数 Datasheet PDF下载

HT48CA0-2图片预览
型号: HT48CA0-2
PDF下载: 下载PDF文件 查看货源
内容描述: 遥控型8位MCU [Remote Type 8-Bit MCU]
分类和应用: 微控制器和处理器外围集成电路遥控LTE
文件页数/大小: 32 页 / 235 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT48RA0-2/HT48CA0-2  
Watchdog Timer - WDT  
Power Down Operation - HALT  
The clock source of the WDT is implemented by instruc-  
tion clock (system clock divided by 4). The clock source  
is processed by a frequency divider and a prescaller to  
yield various time out periods.  
The HALT mode is initialized by the HALT instruction  
and results in the following...  
·
·
The system oscillator turns off and the WDT stops.  
The contents of the on-chip RAM and registers remain  
unchanged.  
Clock Source  
WDT time out period =  
2n  
·
·
·
WDT prescaler are cleared.  
All I/O ports maintain their original status.  
The PDF flag is set and the TO flag is cleared.  
Where n= 8~11 selected by code option.  
This timer is designed to prevent a software malfunction  
or sequence jumping to an unknown location with un-  
predictable results. The Watchdog Timer can be dis-  
abled by code option. If the Watchdog Timer is disabled,  
all the executions related to the WDT result in no opera-  
tion and the WDT will lose its protection purpose. In this  
situation the logic can only be restarted by an external  
logic.  
The system can quit the HALT mode by means of an ex-  
ternal reset or an external falling edge signal on port B.  
An external reset causes a device initialization. Exam-  
ining the TO and PDF flags, the reason for chip reset  
can be determined. The PDF flag is cleared when the  
system powers up or execute the CLR WDT instruction  
and is set when the HALT instruction is executed. The  
TO flag is set if the WDT time-out occurs, and causes a  
wake-up that only resets the PC (Program Counter) and  
SP, the others keep their original status.  
A WDT overflow under normal operation will initialize ²chip  
reset² and set the status bit ²TO². To clear the contents of  
the WDT prescaler, three methods are adopted; external  
reset (a low level to RES), software instructions, or a HALT  
instruction. There are two types of software instructions.  
One type is the single instruction ²CLR WDT², the other  
type comprises two instructions, ²CLR WDT1² and ²CLR  
WDT2². Of these two types of instructions, only one can  
be active depending on the code option - ²CLR WDT  
times selection option². If the ²CLR WDT² is selected (i.e..  
CLR WDT times equal one), any execution of the CLR  
WDT instruction will clear the WDT. In case ²CLR WDT1²  
and ²CLR WDT2² are chosen (i.e.. CLR WDT times equal  
two), these two instructions must be executed to clear the  
WDT; otherwise, the WDT may reset the chip due to a  
time-out.  
The port B wake-up can be considered as a continuation  
of normal execution. Each bit in port B can be independ-  
ently selected to wake up the device by the code option.  
Awakening from an I/O port stimulus, the program will  
resume execution of the next instruction.  
Once a wake-up event(s) occurs, it takes 1024 tSYS  
(system clock period) to resume normal operation. In  
other words, a dummy cycle period will be inserted after  
the wake-up.  
To minimize power consumption, all I/O pins should be  
carefully managed before entering the HALT status.  
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Watchdog Timer  
Rev. 1.50  
7
July 23, 2004