HT48RA0-2/HT48CA0-2
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
VDD
IDD
Operating Voltage
2.0
¾
3.6
1.5
V
mA
mA
V
¾
¾
0.7
¾
¾
¾
¾
¾
1.9
8
No load, fSYS=4MHz
Operating Current
3V
ISTB
VIL1
VIH1
VIL2
VIH2
VLVR
IOL
Standby Current
3V No load, system HALT
1
¾
0.3VDD
VDD
0.4VDD
VDD
2.0
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
I/O Ports Sink Current
3V
3V
3V
3V
¾
0
¾
¾
¾
¾
¾
0.7VDD
0
V
V
0.9VDD
V
V
¾
4
VOL=0.1VDD
VOH=0.9VDD
3V
mA
mA
kW
¾
IOH
PC0/REM Output Source Current 3V
-2
20
-4
60
¾
RPH
Pull-high Resistance
3V
100
¾
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
3V
¾
Conditions
fSYS
tRES
System Clock
400
1
4000
kHz
¾
¾
¾
¾
External Reset Low Pulse Width
¾
ms
Power-up, reset or wake-up
from HALT
tSST
tLVR
tSYS
ms
System Start-up Timer Period
Low Voltage Width to Reset
1024
¾
¾
¾
¾
¾
1
¾
¾
Note: tSYS=1/fSYS
Functional Description
Execution Flow
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
The HT48RA0-2/HT48CA0-2 system clock can be de-
rived from a crystal/ceramic resonator oscillator. It is in-
ternally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
S
y
s
t
e
m
C
l
o
c
k
I
n
s
t
r
u
c
t
i
o
n
C
y
c
l
e
P
C
P
C
+
1
P
C
+
2
P
C
F
e
t
c
h
I
N
S
T
(
P
C
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
-
1
)
F
e
t
c
h
I
N
S
T
(
P
C
+
1
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
)
F
e
t
c
h
I
N
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution Flow
Rev. 1.50
3
July 23, 2004
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
