HT48RA0-2/HT48CA0-2
Carrier
struction. PB0~PB1 have the same structure with PA,
while PB2~PB5 can only be used for input operation
(Schmitt trigger with pull-high resistors). PC is only
one-bit output port shares the pin with carrier output. If
the level option is selected, the PC is CMOS output.
The HT48RA0-2/HT48CA0-2 provides a carrier output
which shares the pin with PC0. It can be selected to be a
carrier output (REM) or level output pin (PC0) by code
option. If the carrier output option is selected, setting
PC0=²0² to enable carrier output and setting PC0=²1² to
disable it at low level output.
Both PA and PB for the input operation, these ports are
non-latched, that is, the inputs should be ready at the T2
rising edge of the instruction ²MOV A, [m]² (m=12H or
14H). For PA, PB0~PB1 and PC output operation, all
data are latched and remain unchanged until the output
latch is rewritten.
The clock source of the carrier is implemented by in-
struction clock (system clock divided by 4) and pro-
cessed by a frequency divider to yield various carry
frequency.
When the PA and PB0~PB1 is used for input operation,
it should be noted that before reading data from pads, a
²1² should be written to the related bits to disable the
NMOS device. That is, the instruction ²SET [m].i² (i=0~7
for PA, i=0~1 for PB) is executed first to disable related
NMOS device, and then ²MOV A, [m]² to get stable data.
Clock Source
Carry Frequency=
m´2n
where m=2 or 3 and n=0~3, both are selected by code
option. If m=2, the duty cycle of the carrier output is 1/2
duty. If m=3, the duty cycle of the carrier output can be
1/2 duty or 1/3 duty also determined by code option (with
the exception of n=0).
After chip reset, PA and PB remain at a high level input
line while PC remain at high level output, if the level op-
tion is selected.
Detailed selection of the carrier duty is shown below:
m´2n
Duty Cycle
Each bit of PA, PB0~PB1 and PC output latches can be
set or cleared by the ²SET [m].i² and ²CLR [m].i²
(m=12H, 14H or 16H) instructions respectively.
2, 4, 8, 16
3
1/2
1/3
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR [m]²,
²CPL [m]², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or to the
accumulator.
6, 12, 24
1/2 or 1/3
The following table shows examples of carrier fre-
quency selection.
m´2n
fSYS
fCARRIER
37.92kHz
56.9kHz
Duty
1/3 only
1/2 only
3
2
Each line of PB has a wake-up capability to the device
by code option. The highest seven bits of PC are not
physically implemented, on reading them a ²0² is re-
turned and writing results in a no-operation.
455kHz
Input/Output Ports
Note: The bit 6 and Bit 7 the PB register (14H) are un-
used in the HT48RA0-2/HT48CA0-2, any read from that
will return the value ²0². User Should be very careful in
transferring the program from the HT48RA0A or
HT48RA0-1/HT48CA0-1 device to the HT48RA0-2/
HT48CA0-2 device.
There are an 8-bit bidirectional input/output port, a 4-bit
input with 2-bit I/O port and one-bit output port in the
HT48RA0-2/HT48CA0-2, labeled PA, PB and PC which
are mapped to [12H], [14H], [16H] of the RAM, respec-
tively. Each bit of PA can be selected as NMOS output or
Schmitt trigger with pull-high resistor by software in-
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Carrier/Level Output
Rev. 1.50
9
July 23, 2004
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
