HT46R064G/065G/0662G
Enhanced A/D Type 8-Bit OTP MCU with OPA
low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter
will stop counting. It is important to note that in the pulse width capture Mode, the enable bit is
automatically reset to zero when the external control signal on the external timer pin returns to its
original level, whereas in the other two modes the enable bit can only be reset to zero under program
control.
The residual value in the Timer/Event Counter, which can now be read by the program, therefore
represents the length of the pulse received on the TCn pin. As the enable bit has now been reset, any
further transitions on the external timer pin will be ignored. The timer cannot begin further pulse width
capture until the enable bit is set high again by the program. In this way, single shot pulse
measurements can be easily made.
It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the
external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an
interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the
preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event
Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero.
As the TCn pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse width
capture pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in the pulse width capture Mode, the second is
to ensure that the port control register configures the pin as an input.
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Pulse Width Capture Mode Timing Chart (TnEG=0)
Prescaler
Bits T0PSC0~T0PSC2 of the TMR0C register can be used to define a division ratio for the internal
clock source of the Timer/Event Counter enabling longer time out periods to be setup.
PFD Function
The Programmable Frequency Divider provides a means of producing a variable frequency output
suitable for applications, such as piezo-buzzer driving or other interfaces requiring a precise frequency
generator.
The Timer/Event Counter overflow signal is the clock source for the PFD function, which is controlled
by PFDCS bit in CTRL0. For applicable devices the clock source can come from either Timer/Event
Counter 0 or Timer/Event Counter 1. The output frequency is controlled by loading the required values
into the timer prescaler and timer registers to give the required division ratio. The counter will begin to
count-up from this preload register value until full, at which point an overflow signal is generated,
causing both the PFD outputs to change state. The counter will then be automatically reloaded with the
preload register value and continue counting-up.
If the CTRL0 register has selected the PFD function, then for PFD output to operate, it is essential for
the corresponding Port control register, to setup the PFD pins as outputs. The corresponding I/O pin
data bit must be set high to activate the PFD. The output data bits can be used as the on/off control bit
for the PFD outputs. Note that the PFD outputs will all be low if the output data bit is cleared to zero.
Rev. 1.00
60
March 3, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
