HT46R064G/065G/0662G
Enhanced A/D Type 8-Bit OTP MCU with OPA
Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer TCn pin,
can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit
pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown.
Bit7
Bit6
Control Register Operating Mode
Select Bits for the Event Counter Mode
0
1
In this mode, the external timer TCn pin, is used as the Timer/Event Counter clock source, however it
is not divided by the internal prescaler. After the other bits in the Timer Control Register have been
setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the
Timer/Event Counter to run. If the Active Edge Select bit, TnEG, which is bit 3 of the Timer Control
Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a
low to high transition. If the TnEG is high, the counter will increment each time the external timer pin
receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already loaded into the preload register and continue
counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit
in the corresponding Interrupt Control Register, is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an
event counter input pin, two things have to happen. The first is to ensure that the Operating Mode
Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode,
the second is to ensure that the port control register configures the pin as an input. It should be noted
that in the event counting mode, even if the microcontroller is in the Idle/Sleep Mode, the Timer/Event
Counter will continue to record externally changing logic events on the timer input TCn pin. As a
result when the timer overflows it will generate a timer interrupt and corresponding wake-up source.
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Event Counter Mode Timing Chart (TnEG=1)
Pulse Width Capture Mode
In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied
to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in
the Timer Control Register must be set to the correct value as shown.
Bit7
Bit6
Control Register Operating Mode
Select Bits for the Pulse Width Capture Mode
1
1
In this mode the internal clock, fSYS, fSYS/4 or the LXT oscillator, is used as the internal clock
determined by which Timer/Event Counter is selected to be used. The internal clock source for the
Timer/Event Counter 0 is further divided by a prescaler, the value of which is determined by the
Prescaler Rate Select bits named T0PSC2~T0PSC0, which are bits 2~0 in the Timer Control Register.
After other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of
the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not
actually start counting until an active edge is received on the external timer pin.
If the Active Edge Select bit TnEG, which is bit 3 of the Timer Control Register, is low, once a high to
low transition has been received on the external timer pin, the Timer/Event Counter will start counting
until the external timer pin returns to its original high level. At this point the enable bit will be
automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select
bit is high, the Timer/Event Counter will begin counting once a low to high transition has been
received on the external timer pin and stop counting when the external timer pin returns to its original
Rev. 1.00
59
March 3, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
