HT46R51/HT46R52
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Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
result lower-order byte register (ADRL;20H), the A/D re-
sult higher-order byte register (ADRH;21H), the A/D
control register (ADCR;22H), the A/D clock setting reg-
ister (ACSR;23H), I/O registers (PA;12H, PB;14H,
PD;18H) and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The remaining space before the 28H is re-
served for future expanded usage and reading these lo-
cations will return the result ²00H². The general purpose
data memory, addressed from 28H to 7FH, is used for
data and control information under instruction com-
mands. All of the data memory areas can handle arith-
metic, logic, increment, decrement and rotate
operations directly. Except for some dedicated bits,
each bit in the data memory can be set and reset by
²SET [m].i² and ²CLR [m].i². They are also indirectly ac-
cessible through memory pointer registers (MP0;01H or
MP1;03H).
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO and PDF flags. Addition opera-
tions related to the status register may give different re-
sults from those intended. The TO flag can be affected
only by system power-up, a WDT time-out or executing
the ²HALT² or ²CLR WDT² instruction. The PDF flag can
be affected only by executing the ²HALT² or ²CLR WDT²
instruction or a system power-up.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] ([02H]) will access the data memory
pointed to by MP0 (MP1). Reading location 00H (02H)
itself indirectly will return the result ²00H². Writing indi-
rectly results in no operation. The memory pointer regis-
ters (MP0 and MP1) are 7-bit registers.
The Z, OV, AC, and C flags reflect the status of the latest
operations. On entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status is important, and if the subroutine is likely to
corrupt the status register, the programmer should take
precautions and save it properly.
Accumulator - ACC
The accumulator closely relates to ALU operations. It is
also mapped to location ²05H² of the data memory
which can operate with immediate data. The data move-
ment between two data memories has to pass through
the accumulator.
Interrupts
Arithmetic and Logic Unit - ALU
The device provides an external interrupt, an internal
timer/event counter interrupt, and an A/D converter in-
terrupt. The interrupt control register (INTC;0BH) con-
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
Bit No.
Label
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
0
C
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
4
PDF
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
5
TO
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.40
8
July 12, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
