HT46R47E/HT46C47E
Bit No.
Label
Function
Select the A/D converter clock source.
0, 0: fSYS/2
0
1
ADCS0
ADCS1
0, 1: fSYS/8
1, 0: fSYS/32
1, 1: Undefined
2~6
7
¾
Unused bit, read as ²0².
TEST
For internal test only.
ACSR (23H) Register
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
mov
mov
mov
a,00000001B
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
a,00100000B
ADCR,a
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
set
clr
START
START
START
; reset A/D
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
jmp
mov
mov
mov
mov
polling_EOC
a,ADRH
adrh_buffer,a
a,ADRL
; read conversion result high byte value from the ADRH register
; save result to user defined memory
; read conversion result low byte value from the ADRL register
; save result to user defined memory
adrl_buffer,a
:
:
jmp
start_conversion
; start next A/D conversion
Example: using interrupt method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
mov
a,00000001B
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
ADCR,a
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
set
clr
clr
START
START
START
ADF
; reset A/D
; start A/D
; clear ADC interrupt request flag
Rev. 1.30
19
July 13, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
