HT46R12
Stack Register - STACK
²00H². The general purpose data memory, addressed
from 28H to 7FH is used for data and control information
under instruction commands.
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer register (MP0;01H/MP1;03H).
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0
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0
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0
1
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H
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If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return ad-
dresses are stored).
A
C
C
P
C
L
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B
L
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T
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L
H
0
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H
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F
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H
H
Data Memory - RAM
1
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1
0
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T
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C
The data memory is organized into 115´8 bits, and is di-
vided into two functional groups, namely; special func-
tion registers and general purpose data memory (88´8
bits), most of which are readable/writeable, although
some are read only.
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The special function registers consist of an Indirect ad-
dressing register 0 (00H), a Memory pointer register 0
(MP0;01H), an Indirect addressing register 1 (02H), a
Memory pointer register 1 (MP1;03H), an Accumulator
(;05H), a Program counter lower-order byte register
(PCL;06H), a Table pointer (TBLP;07H), a Table
higher-order byte register (TBLH;08H), a Status register
(STATUS;0AH), an Interrupt control register 0
(INTC0;0BH), a Timer/Event Counter 0 (TMR0;0DH), a
Timer/Event Counter 0 control register (TMR0C;0EH), a
Timer/Event Counter 1 (TMR1;10H), a Timer/Event
Counter 1 control register (TMR1C;11H), Interrupt con-
trol register 1 (INTC1;1EH), the A/D result lower-order
byte register (ADRL;24H), the A/D result higher-order
byte register (ADRH;25H), the A/D control register
(ADCR;26H), the A/D clock setting register
(ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H)
and I/O control registers (PAC;13H, PBC;15H,
PCC;17H), the programmable pulse generator (PPG)
control register (PPG0C;20H), and the programmable
pulse generator timer register (PPGT0;21H). The re-
maining space before the 28H is reserved for future
expansion usage and reading these locations will get a
1
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H
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0
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H
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RAM Mapping
Rev. 1.20
8
February 24, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
