HT46R064B/065B/066B
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter or Time Base requires
microcontroller attention, their corresponding interrupt
will enforce a temporary suspension of the main pro-
gram allowing the microcontroller to direct attention to
their respective needs.
Counter will then be loaded with a new address which
will be the value of the corresponding interrupt vector.
The microcontroller will then fetch its next instruction
from this interrupt vector. The instruction at this vector
will usually be a JMP statement which will jump to an-
other section of program which is known as the interrupt
service routine. Here is located the code to control the
appropriate interrupt. The interrupt service routine must
be terminated with a RETI instruction, which retrieves
the original Program Counter address from the stack
and allows the microcontroller to continue with normal
execution at the point where the interrupt occurred.
The devices contain a single external interrupt and mul-
tiple internal interrupts. The external interrupt is con-
trolled by the action of the external interrupt pin, while
the internal interrupt is controlled by the Timer/Event
Counters and Time Base overflows.
The various interrupt enable bits, together with their as-
sociated request flags, are shown in the following dia-
gram with their order of priority.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by using two regis-
ters, INTC0 and INTC1. By controlling the appropriate
enable bits in this registers each individual interrupt can
be enabled or disabled. Also when an interrupt occurs,
the corresponding request flag will be set by the
microcontroller. The global enable flag if cleared to zero
will disable all interrupts.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, as the EMI bit will be cleared au-
tomatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests oc-
cur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be re-
corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the rou-
tine, to allow interrupt nesting. If the stack is full, the in-
terrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
A Timer/Event Counter overflow, a Time Base event or
an active edge on the external interrupt pin will all gener-
ate an interrupt request by setting their corresponding
request flag, if their appropriate interrupt enable bit is
set. When this happens, the Program Counter, which
stores the address of the next instruction to be exe-
cuted, will be transferred onto the stack. The Program
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B
Interrupt Scheme
Rev. 1.10
59
October 23, 2012
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
