HT46R064B/065B/066B
·
ACSR Register
Bit
Name
R/W
7
TEST
R/W
1
6
ADONB
R/W
0
5
4
3
2
ADCS2
R/W
0
1
ADCS1
R/W
0
0
ADCS0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7
Bit 6
TEST: for test mode use only
ADONB: ADC module power on/off control bit
0: ADC module power on
1: ADC module power off
Note: 1. it is recommended to set ADONB=1 before entering idle/sleep for saving power.
2. ADONB=1 will power down the ADC module.
Bit 5~3
Bit 2~0
unimplemented, read as ²0²
ADCS2~ADCS0: Select A/D converter clock source
000: system clock/2
001: system clock/8
010: system clock/32
011: undefined, can¢t be used.
100: system clock
101: system clock/4
110: system clock/16
111: undefined, can¢t be used.
The START bit in the register is used to start and reset
the A/D converter. When themicrocontroller sets this bit
from low to high and then low again, an analog to digital
conversion cycle will be initiated. When the START bit is
brought from low to high but not low again, the EOCB bit
in the ADCR register will be set to a ²1² and the analog
to digital converter will be reset. It is the START bit that is
used to control the overall start operation of the internal
analog to digital converter.
Controlling the power on/off function of the A/D con-
verter circuitry is implemented using the value of the
ADONB bit.
Although the A/D clock source is determined by the sys-
tem clock fSYS, and by bits ADCS2, ADCS1 and ADCS0,
there are some limitations on the maximum A/D clock
source speed that can be selected. As the minimum value
of permissible A/D clock period, tAD, is 0.5ms, care must be
taken for system clock speeds in excess of 4MHz. For
system clock speeds in excess of 4MHz, the ADCS2,
ADCS1 and ADCS0 bits should not be set to ²000². Doing
so will give A/D clock periods that are less than the mini-
mum A/D clock period which may result in inaccurate A/D
conversion values. Refer to the following table for exam-
ples, where values marked with an asterisk * show where,
depending upon the device, special care must be taken,
as the values may be less than the specified minimum A/D
Clock Period.
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically set to ²0² by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detect-
ing the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates
from the system clock fSYS, is first divided by a division
ratio, the value of which is determined by the ADCS2,
ADCS1 and ADCS0 bits in the ACSR register.
Rev. 1.10
55
October 23, 2012
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
