HT46R232/HT46C232
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PB7
PB7
PB7
PB7
PB7
PB7
PB7
AN7
PB6
PB6
PB6
PB6
PB6
PB6
PB6
AN6
PB5
PB5
PB5
PB5
PB5
PB5
AN5
AN5
PB4
PB4
PB4
PB4
PB4
AN4
AN4
AN4
PB3
PB3
PB3
PB3
AN3
AN3
AN3
AN3
PB2
PB2
PB2
AN2
AN2
AN2
AN2
AN2
PB1
PB1
AN1
AN1
AN1
AN1
AN1
AN1
PB0
AN0
AN0
AN0
AN0
AN0
AN0
AN0
Port B Configuration
Bit No.
Label
Function
Selects the A/D converter clock source
00= system clock/2
0
1
ADCS0
ADCS1
01= system clock/8
10= system clock/32
11= undefined
2~6
7
¾
Unused bit, read as ²0²
TEST
For test mode used only
ACSR (27H) Register
ACS2
ACS1
ACS0
Analog Channel
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
1
0
1
0
1
0
1
Analog Input Channel Selection
Register
ADRL
Bit7
D1
Bit6
Bit5
¾
Bit4
¾
Bit3
¾
Bit2
¾
Bit1
¾
Bit0
¾
D0
D8
ADRH
D9
D7
D6
D5
D4
D3
D2
Note: D0~D9 is A/D conversion result data bit LSB~MSB.
ADRL (24H), ADRH (25H) Register
Rev. 1.50
20
January 21, 2009