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HT46R232(48SSOP-A) 参数 Datasheet PDF下载

HT46R232(48SSOP-A)图片预览
型号: HT46R232(48SSOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO48,]
分类和应用: 可编程只读存储器微控制器光电二极管
文件页数/大小: 48 页 / 354 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT46R232/HT46C232  
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-  
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,  
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.  
Example: using EOCB Polling Method to detect end of conversion  
clr  
EADI  
a,00000001B  
ACSR,a  
a,00100000B  
ADCR,a  
; disable ADC interrupt  
mov  
mov  
mov  
mov  
; setup the ACSR register to select fSYS/8 as the A/D clock  
; setup ADCR register to configure Port PB0~PB3 as A/D inputs  
; and select AN0 to be connected to the A/D converter  
:
:
; As the Port B channel bits have changed the following START  
; signal (0-1-0) must be issued within 10 instruction cycles  
:
Start_conversion:  
clr  
set  
clr  
START  
START  
START  
; reset A/D  
; start A/D  
Polling_EOC:  
sz  
EOCB  
; poll the ADCR register EOCB bit to detect end of A/D conversion  
; continue polling  
; read conversion result high byte value from the ADRH register  
; save result to user defined memory  
; read conversion result low byte value from the ADRL register  
; save result to user defined memory  
jmp  
mov  
mov  
mov  
mov  
polling_EOC  
a,ADRH  
adrh_buffer,a  
a,ADRL  
adrl_buffer,a  
:
:
start_conversion  
jmp  
; start next A/D conversion  
Example: using interrupt method to detect end of conversion  
; disable ADC interrupt  
clr  
mov  
mov  
EADI  
a,00000001B  
ACSR,a  
; setup the ACSR register to select fSYS/8 as the A/D clock  
mov  
mov  
a,00100000B  
ADCR,a  
:
; setup ADCR register to configure Port PB0~PB3 as A/D inputs  
; and select AN0 to be connected to the A/D converter  
; As the Port B channel bits have changed the following START  
; signal (0-1-0) must be issued within 10 instruction cycles  
:
Start_conversion:  
clr  
set  
clr  
START  
START  
START  
ADF  
; reset A/D  
; start A/D  
clr  
; clear ADC interrupt request flag  
; enable ADC interrupt  
; enable global interrupt  
set  
set  
EADI  
EMI  
:
:
:
; ADC interrupt service routine  
ADC_ISR:  
mov  
mov  
mov  
acc_stack,a  
a,STATUS  
status_stack,a  
:
; save ACC to user defined memory  
; save STATUS to user defined memory  
:
mov  
mov  
mov  
mov  
clr  
a,ADRH  
adrh_buffer,a  
a,ADRL  
adrl_buffer,a  
START  
START  
START  
:
; read conversion result high byte value from the ADRH register  
; save result to user defined register  
; read conversion result low byte value from the ADRL register  
; save result to user defined register  
set  
clr  
; reset A/D  
; start A/D  
:
EXIT_INT_ISR:  
mov  
mov  
mov  
reti  
a,status_stack  
STATUS,a  
a,acc_stack  
; restore STATUS from user defined memory  
; restore ACC from user defined memory  
Rev. 1.50  
21  
January 21, 2009  
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