HT46R232/HT46C232
Input/Output Ports
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
There are 40 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC, PD and PF,
which are mapped to the data memory of [12H], [14H],
[16H], [18H] and [28H] respectively. All of these I/O ports
can be used for input and output operations. For input
operation, these ports are non-latching, that is, the in-
puts must be ready at the T2 rising edge of instruction
²MOV A,[m]² (m=12H, 14H, 16H, [18H] or 28H). For out-
put operation, all the data is latched and remains un-
changed until the output latch is rewritten.
Each line of port A has the capability of waking-up the
device. Each I/O port has a pull-high option. Once the
pull-high option is selected, the I/O port has a pull-high
resistor, otherwise, there¢s none. Take note that a
non-pull-high I/O port operating in input mode will cause
a floating state.
The PA3 and PA5 are pin-shared with the PFD and INT
pins respectively. If the PFD option is selected, the out-
put signal in output mode of PA3 will be the PFD signal
generated by timer/event counter overflow signal. The
input mode always remain in its original functions. Once
the PFD option is selected, the PFD output signal is con-
trolled by PA3 data register only. Writing ²1² to PA3 data
register will enable the PFD output function and writing 0
will force the PA3 to remain at ²0². The I/O functions of
PA3 are shown below.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PFC) to control the input/output configura-
tion. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor structures
can be reconfigured dynamically under software control.
To function as an input, the corresponding latch of the
control register must write ²1². The input source also de-
pends on the control register. If the control register bit is
²1², the input will read the pad state. If the control regis-
ter bit is ²0², the contents of the latches will move to the
internal bus. The latter is possible in the ²read-modify-
write² instruction.
I/O
I/P
O/P
I/P
O/P
Mode (Normal) (Normal)
(PFD)
(PFD)
Logical
Input
Logical
Output
Logical
Input
PFD
PA3
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H, 19H and 29H.
(Timer on)
Note: The PFD frequency is the timer/event counter
overflow frequency divided by 2.
After a chip reset, these input/output lines remain at high
levels or floating state (depends on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H 18H or 28H) instructions.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1/PD2/PD3. If the PWM
function is enabled, the PWM0/PWM1/PWM2/PWM3
signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/
PD2/PD3 is operating in output mode). The I/O func-
tions of PD0/PD1/PD2/PD3 are as shown.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
V
D
D
C
o
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B
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P
U
P
A
0
3
4
5
6
7
0
~
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P
A
2
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P
B
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A
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0
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7
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A
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7
P
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0
~
P
C
7
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4
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P
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W
W
W
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M
M
M
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0
1
2
3
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P
F
7
M
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(
P
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P
A
3
,
P
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~
P
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P
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,
P
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[
P
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2
3
,
,
P
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W
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M
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2
3
]
]
O
P
0
~
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P
7
(
P
A
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)
I
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5
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Input/Output Ports
Rev. 1.50
17
January 21, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
