HT46R232/HT46C232
The bit0~bit2 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of timer/event
counter. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD sig-
nal. The timer prescaler is also used as the PWM counter.
Bit No.
Label
Function
Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
0
1
2
T0PSC0 010: fINT=fSYS/4
T0PSC1 011: fINT=fSYS/8
T0PSC2 100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
3
T0E
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
5
T0ON
Enable/disable timer counting (0=disabled; 1=enabled)
¾
Unused bit, read as ²0²
Defines the operating mode, T0M1, T0M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
T0M0
T0M1
TMR0C (0EH) Register
Bit No.
Label
Function
0~2
¾
Unused bit, read as ²0²
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
3
T1E
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
5
T1ON
Enable/disable timer counting (0=disabled; 1=enabled)
¾
Unused bit, read as ²0²
Defines the operating mode, T1M1, T1M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
T1M0
T1M1
TMR1C (11H) Register
Rev. 1.50
16
January 21, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
