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HT45R37-A(28SSOP-A) 参数 Datasheet PDF下载

HT45R37-A(28SSOP-A)图片预览
型号: HT45R37-A(28SSOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 12MHz, CMOS, PDSO28]
分类和应用: 可编程只读存储器LTE微控制器光电二极管
文件页数/大小: 100 页 / 666 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT45R37  
A/D Clock Period (tAD  
)
ADCS2, ADCS1,  
ADCS0=000  
(fSYS/2)  
ADCS2, ADCS1,  
ADCS0=001  
(fSYS/8)  
ADCS2, ADCS1,  
ADCS0=010  
(fSYS/32)  
ADCS2, ADCS1,  
fSYS  
ADCS0=011  
1MHz  
2MHz  
4MHz  
8MHz  
12MHz  
Undefined  
Undefined  
Undefined  
Undefined  
Undefined  
2ms  
8ms  
4ms  
32ms  
16ms  
8ms  
1ms  
500ns*  
250ns*  
167ns*  
2ms  
1ms  
4ms  
667ns*  
2.67ms  
A/D Clock Period Examples  
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A/D Converter Control Register - ACSR  
A/D Input Pins  
the channel selection bits have changed, then, within a  
time frame of one to ten instruction cycles, the START bit  
in the ADCR register must first be set high and then im-  
mediately cleared to zero. This will ensure that the EOCB  
flag is correctly set to a high condition.  
All of the A/D analog input pins are pin-shared with the  
I/O pins on Port B. Bits PCR2~PCR0 in the ADCR regis-  
ter, determine whether the input pins are setup as nor-  
mal Port B input/output pins or whether they are setup  
as analog inputs. In this way, pins can be changed under  
program control to change their function from normal I/O  
operation to analog inputs and vice versa. Pull-high re-  
sistors, which are setup through register programming,  
apply to the input pins only when they are used as nor-  
mal I/O pins, if setup as A/D inputs the pull-high resistors  
will be automatically disconnected. Note that it is not  
necessary to first setup the A/D pin as an input in the  
PBC port control register to enable the A/D input as  
when the PCR2~PCR0 bits enable an A/D input, the sta-  
tus of the port control register will be overridden. The  
A/D converter has its own power supply pins AVDD and  
AVSS pin. The analog input values must not be allowed  
to exceed the value of AVDD.  
Summary of A/D Conversion Steps  
The following summarises the individual steps that  
should be executed in order to implement an A/D con-  
version process.  
·
Step 1  
Select the required A/D conversion clock by correctly  
programming bits ADCS2, ADCS1 and ADCS0 in the  
register.  
·
Step 2  
Enable the A/D by clearing the in the ACSR register to  
zero.  
·
Step 3  
Select which channel is to be connected to the internal  
A/D converter by correctly programming the  
ACS2~ACS0 bits which are also contained in the reg-  
ister.  
Initialising the A/D Converter  
The internal A/D converter must be initialised in a special  
way. Each time the Port B A/D channel selection bits are  
modified by the program, the A/D converter must be  
re-initialised. If the A/D converter is not initialised after the  
channel selection bits are changed, the EOCB flag may  
have an undefined value, which may produce a false end  
of conversion signal. To initialise the A/D converter after  
·
Step 4  
Select which pins on Port B are to be used as A/D in-  
puts and configure them as A/D input pins by correctly  
programming the PCR2~PCR0 bits in the ADCR reg-  
ister. Note that this step can be combined with Step 2  
into a single ADCR register programming operation.  
Rev. 1.20  
35  
February 25, 2011  
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