HT36M4
The registers¢ status is summarized in the following table:
Reset
WDT Time-out
RES Reset
(Power On) (Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
Register
Program Counter
MP0
0000H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0111
--00 xxxx
-000 0000
xxxx xxxx
xxxx xxxx
00-0 1---
xxxx xxxx
xxxx xxxx
00-0 1---
1111 1111
1111 1111
---- 1111
---- 1111
---- -000
0000H
0000H
0000H
0000H
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
--1u uuuu
-000 0000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
--uu uuuu
-000 0000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
--01 uuuu
-000 0000
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uu-u u---
MP1
ACC
TBLP
TBLH
WDTS
STATUS
INTC
TMR0H
TMR0L
TMR0C
TMR1H
TMR1L
TMR1C
PA
xxxx xxxx
xxxx xxxx
00-0 1---
xxxx xxxx
xxxx xxxx
00-0 1---
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uuuu uuuu
uu-u u---
1111 1111
1111 1111
---- 1111
1111 1111
1111 1111
---- 1111
1111 1111
1111 1111
---- 1111
uuuu uuuu
uuuu uuuu
---- uuuu
PAC
PB
PBC
---- 1111
---- 1111
---- 1111
---- uuuu
PF
---- -000
---- -000
---- -000
---- -uuu
CHAN
FreqNH
FreqNL
AddrH
AddrL
ReH
00-- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
x-xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- --00
uu-- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --00
uu-- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --00
uu-- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --00
uu-- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --uu
ReL
ENV
RVC
DAH
DAL
DAC
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.10
12
March 14, 2007