HT48RA0-3/HT48CA0-3
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
Indirect Addressing Register
I
A
R
M
P
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation to
[00H] accesses the data memory pointed to by MP
(01H). Reading location 00H itself indirectly will return
the result 00H. Writing indirectly results in no operation.
A
C
C
P
C
L
The memory pointer register MP (01H) is a 7-bit register.
Bit 7 of MP is undefined and reading will return the result
²1². Any writing operation to MP will only transfer the
lower 7-bits of data to MP.
T
B
L
P
T
B
L
H
0
0
A
B
H
H
S
T
A
T
U
S
Accumulator
0
0
C
D
H
H
The accumulator closely relates to ALU operations. It is
also mapped to location 05H of the data memory and is
capable of carrying out immediate data operations. Data
movement between two data memory locations has to
pass through the accumulator.
0
E
H
S
p
e
c
i
a
l
P
u
r
p
o
s
e
0
F
H
D
a
t
a
M
e
m
o
r
y
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
P
P
A
B
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions.
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
·
Logic operations (AND, OR, XOR, CPL)
T
T
S
S
R
R
0
1
·
Rotation (RL, RR, RLC, RRC)
1
1
A
B
H
H
C
C
A
A
R
R
L
L
0
1
·
Increment and Decrement (INC, DEC)
·
Branch decision (SZ, SNZ, SIZ, SDZ ....)
1
1
C
D
H
C
C
A
A
R
R
H
H
0
1
H
The ALU not only saves the results of a data operation but
also changes the contents of the status register.
1
E
H
:
U
n
u
s
e
d
1
F
H
R
e
a
d
a
s
"
0
0
"
2
0
H
Status Register - STATUS
G
e
n
e
r
a
l
P
u
r
p
o
s
e
This 8-bit status register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF) and watchdog time-out
flag (TO). It also records the status information and con-
trols the operation sequence.
D
a
t
a
M
e
m
o
r
y
(
3
2
B
y
t
e
s
)
3
F
H
RAM Mapping
Bit No.
Label
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
0
C
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF
is set by executing the HALT instruction.
4
PDF
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is
set by a WDT time-out.
5
TO
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev.1.10
6
October 12, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
