Port A Data Direction Register (PADDR)
Bit
7
6
5
4
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PADDR is an 8-bit register that controls the input/output direction of each pin in port A. A pin
functions as an output pin if the corresponding PADDR bit is set to 1, and as an input pin if this bit
is cleared to 0.
PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values, so if a transition to software standby mode occurs while a PADDR bit
is set to 1, the corresponding pin remains in the output state.
Port A Output Data Register (PAODR)
Bit
7
PA7
0
6
PA6
0
5
PA5
0
4
PA4
0
3
PA3
0
2
PA2
0
1
PA1
0
0
PA0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PAODR is an 8-bit register that stores data for pins PA7 to PA0. PAODR can always be written to
and read, regardless of the PADDR settings.
PAODR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
Port A Input Data Register (PAPIN)
Bit
7
6
5
4
3
2
1
0
PA7
—*
R
PA6
—*
R
PA5
—*
R
PA4
—*
R
PA3
—*
R
PA2
—*
R
PA1
—*
R
PA0
—*
R
Initial value
Read/Write
Note: * Depends on the levels of pins PA7 to PA0.
When PAPIN is read, the pin states are always read.
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HITACHI [ HITACHI SEMICONDUCTOR ]
