Port 9 Data Direction Register (P9DDR)
Bit
7
6
5
4
3
2
1
0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
Modes 1 and 2
Initial value
Read/Write
Mode 3
0
1
0
0
0
0
0
0
W
—
W
W
W
W
W
W
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P9DDR is an 8-bit register that controls the input/output direction of each pin in port 9. A pin
functions as an output pin if the corresponding P9DDR bit is set to 1, and as an input pin if this bit
is cleared to 0. In modes 1 and 2, P96DDR is fixed at 1 and cannot be modified.
P9DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P9DDR is initialized by a reset and in hardware standby mode. The initial value is H'40 in modes
1 and 2, and H'00 in mode 3. In software standby mode P9DDR retains its existing values, so if a
transition to software standby mode occurs while a P9DDR bit is set to 1, the corresponding pin
remains in the output state.
Port 9 Data Register (P9DR)
Bit
7
P97
0
6
5
P95
0
4
P94
0
3
P93
0
2
P92
0
1
P91
0
0
P90
0
P96
—*
R
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Determined by the level at pin P96.
P9DR is an 8-bit register that stores data for pins P97 to P90. When a P9DDR bit is set to 1, if port
9 is read, the value in P9DR is obtained directly, regardless of the actual pin state, except for P96.
When a P9DDR bit is cleared to 0, if port 9 is read the pin state is obtained. This also applies to
pins used by on-chip supporting modules and for bus control signals. P96 always returns the pin
state.
P9DR pins other than P96 are initialized to 0 by a reset and in hardware standby mode. In software
standby mode it retains its existing values.
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HITACHI [ HITACHI SEMICONDUCTOR ]
