7.12.2 Register Configuration and Descriptions
Table 7.23 summarizes the port B registers.
Table 7.23 Port B Registers
Name
Abbreviation
PBDDR
Read/Write
Initial Value
H'00
Address
H'FFBE
H'FFBC
H'FFBD
Port B data direction register
Port B output data register
Port B input data register
W
PBODR
R/W
R
H'00
PBPIN
Undetermind
Note: The port B data direction register (PBDDR) and port 7 input data register 7 (P7PIN) have
the same address.
Port B Data Direction Register (PBDDR)
Bit
7
6
5
4
3
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PBDDR is an 8-bit register that controls the input/output direction of each pin in port B. A pin
functions as an output pin if the corresponding PBDDR bit is set to 1, and as an input pin if this bit
is cleared to 0.
PBDDR is a write-only register. Read data is invalid. If read, the values of the port 7 data input
register (P7PIN) are returned, indicating the pin levels of port 7.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values, so if a transition to software standby mode occurs while a PBDDR bit
is set to 1, the corresponding pin remains in the output state.
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HITACHI [ HITACHI SEMICONDUCTOR ]
