Description
Section
Page
Item
(see Manual for details)
21.1.7 Flash Memory
Operating Modes
504
Figure 21.2 Flash Memory
Related State Transitions
“SWE” amended to
“FLSHE”.
505
506
Figure 21.3 Boot Mode
Procedure 2 amended.
Procedure 2 amended.
Figure 21.4 User
Programming Mode (Example)
21.2.3 Erase Block
Register 2 (EBR2)
511
516
517
Bit 7 * and Note
description added.
21.3.1 Boot Mode
RAM Area Allocation in Boot
Mode
Description amended.
Figure 21.9 RAM Areas in
Boot Mode
Amended
Notes on Use of Boot Mode
5 description amended.
21.4 to 21.4.4
520 to 524
528
Entire description
amended.
21.5.1 Writer Mode
Setting
* and Note description
added.
21.5.3 Operation in
Writer Mode
538Figure
21.22
Note amendSetdatus
Rea
Mode Timing Waveforms
Table 21.19 Status Read
Mode Return Codes
21.6 Flash Memory
Programming and Erasing
Precautions
540
541
(1) Program with the specified Description amended.
voltage and timing
Table 21.22 Area Accessed in FLSHE = 1 mode 2
Each Mode with FLSHE = 0
and FLSHE = 1
amended
22.3.5 Application Note
2 description deleted.
23 Electrical
Characteristics
553 to 604
579
Heading number
amended
23.3 Electrical
Characteristics
(H8/3437SF Low-Voltage
Version)
Entire description newly
added.
B.2 Function
665
I2C Bus Control Register
Bit 2 to 0: I2C Transfer Rate
Select
Table amended and note
added
HITACHI [ HITACHI SEMICONDUCTOR ]
