Contents
Section 1 Overview............................................................................................................
1.1 Overview............................................................................................................................
1.2 Block Diagram ...................................................................................................................
1.3 Pin Assignments and Functions .........................................................................................
1.3.1 Pin Arrangement...................................................................................................
1.3.2 Pin Functions ........................................................................................................
1
1
5
6
6
7
Section 2 CPU..................................................................................................................... 19
2.1 Overview............................................................................................................................ 19
2.1.1 Features................................................................................................................. 19
2.1.2 Address Space....................................................................................................... 20
2.1.3 Register Configuration.......................................................................................... 20
2.2 Register Descriptions ......................................................................................................... 21
2.2.1 General Registers.................................................................................................. 21
2.2.2 Control Registers .................................................................................................. 21
2.2.3 Initial Register Values .......................................................................................... 22
2.3 Data Formats...................................................................................................................... 23
2.3.1 Data Formats in General Registers ....................................................................... 24
2.3.2 Memory Data Formats.......................................................................................... 25
2.4 Addressing Modes.............................................................................................................. 26
2.4.1 Addressing Mode.................................................................................................. 26
2.4.2 Calculation of Effective Address.......................................................................... 28
2.5 Instruction Set.................................................................................................................... 32
2.5.1 Data Transfer Instructions .................................................................................... 34
2.5.2 Arithmetic Operations .......................................................................................... 36
2.5.3 Logic Operations .................................................................................................. 37
2.5.4 Shift Operations.................................................................................................... 37
2.5.5 Bit Manipulations.................................................................................................. 39
2.5.6 Branching Instructions.......................................................................................... 44
2.5.7 System Control Instructions.................................................................................. 46
2.5.8 Block Data Transfer Instruction............................................................................ 47
2.6 CPU States ......................................................................................................................... 49
2.6.1 Overview............................................................................................................... 49
2.6.2 Program Execution State ...................................................................................... 50
2.6.3 Exception-Handling State..................................................................................... 50
2.6.4 Power-Down State................................................................................................ 51
2.7 Access Timing and Bus Cycle ........................................................................................... 51
2.7.1 Access to On-Chip Memory (RAM and ROM).................................................... 51
2.7.2 Access to On-Chip Register Field and External Devices ..................................... 53
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HITACHI [ HITACHI SEMICONDUCTOR ]
