Page
464 to 466
475, 476
Item
16.3.3 Master Receive
Operation
16.3.10 Sample Flowchart
Revision (See Manual for Details)
Completely amended
Figure 16.14 Flowchart for Master Transmit Mode
(Example)
Figure 16.15 Flowchart for Master Receive Mode
(Example)
completely amended
478
16.3.11 Initialization of
Internal State
Description amended
Executed in accordance with the setting of bits CLR3 to
CLR0 in the DDCSWR register or clearing ICE bit
•
•
Notes on Start Condition Issuance for Retransmission
Notes I
2
C Bus Interface Stop Condition Instruction
Issuance
484
16.4 Usage Notes
added
522
541
19.2.3 A/D Control Register Bits 5 to 0 description amended
(ADCR)
20.3.2 Single-Chip Mode
Description amended
(Modes 2 and 3 (EXPE=0)) Undefined values are always read from these bits, and
writing is invalid.
21. ROM
Description of ROM is added due to the introduction of
the H8S/2138 and H8S/2134 A-mask version
21. ROM (Mask ROM version, H8S/2138F-ZTAT,
H8S/2134F-ZTAT, and H8S/2132F-ZTAT)
22. ROM (H8S/2138F-ZTAT A-mask version and
H8S/2134F-ZTAT A-mask version)
548
21.4.3 Flash Memory
Operating Modes
Figure 21.3 Flash Memory Mode Transitions
Bit name amended between user mode and user program
mode
—
557
562
573
585
21.5.4 Serial/Timer Control Bit 7 description amended
Register (STCR)
21.6.1 Boot Mode
Figure 21.10 RAM Areas in Boot Mode
added
21.10.1 Programmer Mode Notes added
Setting
21.11 Flash Memory
Programming and Erasing
Precautions
Description amended
HITACHI [ HITACHI SEMICONDUCTOR ]
