Page
135
138
139
Item
6.2.2 Wait State Control
Register (WSCR)
6.3.2 Advanced Mode
6.3.4 I/O Select Signal
Revision (See Manual for Details)
Bit 7 description amended
Description amended due to the addition of the
H8S/2138F-ZTAT A mask version.
Table 6.4
IOS
Signal Output Range
Note added
Figure 6.7 Example of Wait State Insertion Timing
WR
timing amended
Table 9.2 PWM Timer Module Registers
Note 2 added
Table 10.2 Register Configuration
Note 2 amended
145
233
6.4.5 Wait Control
9.1.4 Register
Configuration
10.1.4 Register
Configuration
245
278
283
11.3.5 Timing of Input
Figure 11.11 Setting of Input Capture Flag (ICFA/B/C/D)
Capture Flag (ICF) Setting ICRA/B/C/D timing amended
11.6 Usage Note
Figure 11.21 Contention between OCRAR/OCRAF Write
and Compare-Match (When Automatic Addition Function
Is Used) added
302
312 to
313
335
354
364
438
445
449
455
461
462 to 464
12.2.6. Serial/Timer Control Bit 7 description amended
Register (STCR)
12.3.6 Input Capture
Operation
13.3.1 PWM Decoding
(PDC Signal Generation)
Added
Figure 13.2 Timing Chart for PWM Decoding amended
14.2.2 Timer Control/Status Bit 7: Note added
Register (TCSR)
15.1.1 Features
16.2.1 I
2
C Bus Data
Register (ICDR)
16.2.5 I
2
C Bus Control
Register (ICCR)
Capability of transmit and receive clock output description
added
TDRE: 1 description amended
Bit 7 description amended
Bit 1 description amended
16.2.6 I
2
C Bus Status
Register (ICSR)
Bit 0 description amended
16.3.1 I
2
C Bus Data Format Figure 16.4 Formatless added
16.3.2 Master Transmit
Operation
Completely amended
HITACHI [ HITACHI SEMICONDUCTOR ]
