2.8.6 Power-Down State ................................................................................................
2.9 Basic Timing......................................................................................................................
2.9.1 Overview...............................................................................................................
2.9.2 On-Chip Memory (ROM, RAM) .........................................................................
2.9.3 On-Chip Supporting Module Access Timing.......................................................
2.9.4 External Address Space Access Timing...............................................................
2.10 Usage Note.........................................................................................................................
2.10.1 TAS Instruction ....................................................................................................
2.10.2 STM/LDM Instruction..........................................................................................
62
63
63
63
65
66
66
66
67
Section 3
3.1
MCU Operating Modes
................................................................................. 69
69
69
70
70
70
71
73
74
75
75
75
76
76
76
3.2
3.3
3.4
3.5
Overview............................................................................................................................
3.1.1 Operating Mode Selection ....................................................................................
3.1.2 Register Configuration .........................................................................................
Register Descriptions.........................................................................................................
3.2.1 Mode Control Register (MDCR) ..........................................................................
3.2.2 System Control Register (SYSCR).......................................................................
3.2.3 Bus Control Register (BCR).................................................................................
3.2.4 Serial Timer Control Register (STCR).................................................................
Operating Mode Descriptions ............................................................................................
3.3.1 Mode 1 ..................................................................................................................
3.3.2 Mode 2 ..................................................................................................................
3.3.3 Mode 3 ..................................................................................................................
Pin Functions in Each Operating Mode.............................................................................
Memory Map in Each Operating Mode.............................................................................
Section 4
4.1
Exception Handling
........................................................................................ 87
87
87
87
88
90
90
90
92
93
94
95
96
4.2
4.3
4.4
4.5
4.6
Overview............................................................................................................................
4.1.1 Exception Handling Types and Priority ...............................................................
4.1.2 Exception Handling Operation .............................................................................
4.1.3 Exception Sources and Vector Table ...................................................................
Reset...................................................................................................................................
4.2.1 Overview...............................................................................................................
4.2.2 Reset Sequence.....................................................................................................
4.2.3 Interrupts after Reset.............................................................................................
Interrupts ............................................................................................................................
Trap Instruction .................................................................................................................
Stack Status after Exception Handling ..............................................................................
Notes on Use of the Stack..................................................................................................
Section 5
5.1
ii
Interrupt Controller
......................................................................................... 97
Overview............................................................................................................................ 97
5.1.1 Features................................................................................................................. 97
HITACHI [ HITACHI SEMICONDUCTOR ]
