Page
74
77
Item
3.2.4 Serial Timer Control
Register (STCR)
3.5 Memory Map in Each
Operating Mode
Revision (See Manual for Details)
Bit 7 and bit 6 description amended
Description added
Do not access the reserved area and ...when these
regions are accessed.
Figure 3.2 H8S/2138 F-ZTAT A-mask Version Memory
Map in Each Operating Mode added
79, 80
87
4.1.1 Exception Handling
Types and Priority
4.3 Interrupts
Table 4.1 Exception Types and Priority
Trace description amended
Description amended
Interrupts other than NMI and address break
93
96
97
4.6 Notes on Use of the
Stack
5.1.1 Features
Figure 4.6 Operation when SP Value is Odd amended
Priorities settable with ICR description amended
All interrupts except NMI and address break
98
5.1.2 Block Diagram
Figure 5.1 Block Diagram of Interrupt Controller
Internal interrupt requests amended
99
5.1.4 Register
Configuration
5.2.2 Interrupt Control
Registers A to C (ICRA to
ICRC)
5.2.5 IRQ status register
5.2.6 Keyboard Matrix
Interrupt Mask Register
(KMIMR)
5.3.1 External Interrupts
Table 5.2 Interrupt Controller Registers
Note 3 amended
Description amended
Interrupts other than NMI and address break
Note added
Description amended
Bits 7 to 0 Note amended
IRQ7 to IRQ0 Interrupts: description added
When the
IRQ6
pin is assigned as the IRQ6 interrupt
input pin, then set the KMIMR6 bit to 0.
101
104
105
109
116
5.5.1 Interrupt Control
Modes and Interrupt
Operation
Description amended
NMI and address break interrupts
Table 5.6 Interrupts Selected in Each Interrupt Control
Mode
Address break interrupts added
117
121
5.5.3 Interrupt Control
Mode 1
Address break Interrupts description added
HITACHI [ HITACHI SEMICONDUCTOR ]
