5.2
5.3
5.4
5.5
5.6
5.7
5.1.2 Block Diagram......................................................................................................
5.1.3 Pin Configuration .................................................................................................
5.1.4 Register Configuration .........................................................................................
Register Descriptions.........................................................................................................
5.2.1 System Control Register (SYSCR).......................................................................
5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................
5.2.3 IRQ Enable Register (IER)...................................................................................
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL).....................................
5.2.5 IRQ Status Register (ISR) ....................................................................................
5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR)..........................................
5.2.7 Address Break Control Register (ABRKCR).......................................................
5.2.8 Break Address Registers A, B, C (BARA, BARB, BARC).................................
Interrupt Sources................................................................................................................
5.3.1 External Interrupts ................................................................................................
5.3.2 Internal Interrupts .................................................................................................
5.3.3 Interrupt Exception Vector Table.........................................................................
Address Breaks ..................................................................................................................
5.4.1 Features.................................................................................................................
5.4.2 Block Diagram......................................................................................................
5.4.3 Operation ..............................................................................................................
5.4.4 Usage Notes ..........................................................................................................
Interrupt Operation.............................................................................................................
5.5.1 Interrupt Control Modes and Interrupt Operation ................................................
5.5.2 Interrupt Control Mode 0......................................................................................
5.5.3 Interrupt Control Mode 1......................................................................................
5.5.4 Interrupt Exception Handling Sequence...............................................................
5.5.5 Interrupt Response Times.....................................................................................
Usage Notes .......................................................................................................................
5.6.1 Contention between Interrupt Generation and Disabling.....................................
5.6.2 Instructions that Disable Interrupts.......................................................................
5.6.3 Interrupts during Execution of EEPMOV Instruction ..........................................
DTC Activation by Interrupt .............................................................................................
5.7.1 Overview...............................................................................................................
5.7.2 Block Diagram......................................................................................................
5.7.3 Operation ..............................................................................................................
98
99
99
100
100
101
102
102
103
104
106
107
108
108
109
110
113
113
113
114
114
116
116
119
121
124
126
127
127
128
128
129
129
129
130
Section 6
6.1
Bus Controller
.................................................................................................. 131
131
131
132
133
133
134
iii
6.2
Overview............................................................................................................................
6.1.1 Features.................................................................................................................
6.1.2 Block Diagram......................................................................................................
6.1.3 Pin Configuration .................................................................................................
6.1.4 Register Configuration .........................................................................................
Register Descriptions.........................................................................................................
HITACHI [ HITACHI SEMICONDUCTOR ]
