6.3
6.4
6.5
6.6
6.7
6.2.1 Bus Control Register (BCR).................................................................................
6.2.2 Wait State Control Register (WSCR)...................................................................
Overview of Bus Control...................................................................................................
6.3.1 Bus Specifications ................................................................................................
6.3.2 Advanced Mode....................................................................................................
6.3.3 Normal Mode........................................................................................................
6.3.4 I/O Select Signal...................................................................................................
Basic Bus Interface ............................................................................................................
6.4.1 Overview...............................................................................................................
6.4.2 Data Size and Data Alignment .............................................................................
6.4.3 Valid Strobes ........................................................................................................
6.4.4 Basic Timing.........................................................................................................
6.4.5 Wait Control .........................................................................................................
Burst ROM Interface .........................................................................................................
6.5.1 Overview...............................................................................................................
6.5.2 Basic Timing.........................................................................................................
6.5.3 Wait Control .........................................................................................................
Idle Cycle...........................................................................................................................
6.6.1 Operation ..............................................................................................................
6.6.2 Pin States in Idle Cycle.........................................................................................
Bus Arbitration...................................................................................................................
6.7.1 Overview...............................................................................................................
6.7.2 Operation ..............................................................................................................
6.7.3 Bus Transfer Timing.............................................................................................
134
135
137
137
138
138
139
140
140
140
141
142
145
147
147
147
148
149
149
150
150
150
150
151
Section 7
7.1
Data Transfer Controller [H8S/2138 Series]
.......................................... 153
153
153
154
155
156
156
158
159
159
159
160
160
161
162
163
163
165
7.2
7.3
Overview............................................................................................................................
7.1.1 Features.................................................................................................................
7.1.2 Block Diagram......................................................................................................
7.1.3 Register Configuration .........................................................................................
Register Descriptions.........................................................................................................
7.2.1 DTC Mode Register A (MRA).............................................................................
7.2.2 DTC Mode Register B (MRB) .............................................................................
7.2.3 DTC Source Address Register (SAR) ..................................................................
7.2.4 DTC Destination Address Register (DAR) ..........................................................
7.2.5 DTC Transfer Count Register A (CRA)...............................................................
7.2.6 DTC Transfer Count Register B (CRB) ...............................................................
7.2.7 DTC Enable Registers (DTCER) .........................................................................
7.2.8 DTC Vector Register (DTVECR) ........................................................................
7.2.9 Module Stop Control Register (MSTPCR)...........................................................
Operation ...........................................................................................................................
7.3.1 Overview...............................................................................................................
7.3.2 Activation Sources................................................................................................
iv
HITACHI [ HITACHI SEMICONDUCTOR ]
