HANBit
HDD128M72D18RPW
AC characteristics
(THESE AC CHARACTERISTICS WERE TESTED ON THE COMPONENT)
DDR333@CL=2.5
DDR266A@CL=2.0
-13A
DDR266B@CL=2.5
-13B
PARAMETER
SYMBOL
UNIT NOTE
-16B
MIN
60
MAX
MIN
65
MAX
MIN
65
MAX
Row cycle time
tRC
tRFC
tRAS
ns
ns
ns
Refresh row cycle time
Row active time
72
75
75
42
70K
45
120K
45
120K
/RAS to /CAS delay
tRCD
tRP
tRRD
tWR
tWTR
tCCD
18
18
12
15
1
20
20
15
15
1
20
20
15
15
1
ns
ns
ns
tCK
tCK
tCK
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
1
1
1
CL=2.0
Clock cycle time
7.5
6
12
12
7.5
7.5
12
12
10
12
12
ns
ns
tCK
CL=2.5
7.5
Clock high level width
tCH
tCL
tDQSCK
tAC
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.45
0.45
-0.75
-0.75
-
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.45
0.45
-0.75
-0.75
-
0.55
0.55
+0.75
+0.75
+0.5
1.1
tCK
tCK
ns
ns
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tDSS
ns
tCK
tCK
tCK
ns
12
0.9
0.9
0.9
Read Postamble
0.4
0.6
0.4
0.6
0.4
0.6
CK to valid DQS-in
0.75
0
1.25
0.75
0
1.25
0.75
0
1.25
DQS-in setup time
3
DQS-in hold time
0.25
0.2
0.25
0.2
0.25
0.2
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS-in falling edge to CK rising-setup time
DQS-in falling edge to CK rising hold time
DQS-in high level width
tDSH
tDQSH
tDQSL
tDSC
tIS
0.2
0.2
0.2
0.35
0.35
0.9
0.35
0.35
0.9
0.35
0.35
0.9
DQS-in low level width
DQS-in cycle time
1.1
1.1
Address and Control Input setup time(Fast)
Address and Control Input hold time(Fast)
Address and Control Input setup time(Slow)
0.75
0.75
0.8
0.9
0.9
i,5.7~9
i,5.7~9
i, 6~9
tIH
0.9
0.9
ns
tIS
1.0
1.0
ns
URL : www.hbe.co.kr
7
HANBit Electronics Co.,Ltd.
REV 1.0 (January. 2005)
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
