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HDD128M72D18RPW-16B 参数 Datasheet PDF下载

HDD128M72D18RPW-16B图片预览
型号: HDD128M72D18RPW-16B
PDF下载: 下载PDF文件 查看货源
内容描述: DDR SDRAM模块1024MByte。点击( 128Mx72bit )的基础上, 64Mx8 , 4Banks , 8K参考, 184PIN -DIMM与PLL和注册 [DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 14 页 / 446 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit  
HDD128M72D18RPW  
Input / Output Capacitance  
(VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25°C, f = 100MHz)  
DESCRIPTION  
SYMBOL  
CIN1  
MIN  
9
MAX  
11  
UNITS  
pF  
Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE)  
Input capacitance(CKE0,CKE1)  
CIN2  
9
11  
pF  
Input capacitance(/CS0)  
CIN3  
9
11  
pF  
Input capacitance(CK0~CK2, /CK0~/CK2)  
Input capacitance(DM0~DM7)  
CIN4  
11  
14  
14  
14  
12  
pF  
CIN5  
16  
pF  
Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7)  
Data input/output capacitance (CB0~CB7)  
COUT1  
COUT2  
16  
pF  
16  
pF  
DC Characteristics  
(VDD = 2.7V, T =10°C)  
-16B  
-13A  
-13B  
Symbol  
Unit  
Notes  
(DDR333@CL=2.5)  
(DDR266@CL=2.0)  
(DDR266@CL=2.5)  
IDD0  
IDD1  
2230  
2500  
590  
2010  
2280  
540  
2010  
2280  
540  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2F  
IDD2Q  
IDD3P  
IDD3N  
IDD4R  
IDD4W  
IDD5  
1420  
950  
1290  
900  
1290  
900  
1040  
1690  
2540  
2630  
3130  
590  
990  
990  
1560  
2280  
2330  
2910  
540  
1560  
2280  
2330  
2910  
540  
Normal  
IDD6  
Low  
560  
510  
510  
mA  
mA  
Optional  
Power  
IDD7A  
4520  
4080  
4080  
Notes: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
AC Operating Conditions  
PARAMETER  
STMBOL  
VIH (AC)  
VIL (AC)  
VID (AC)  
VIX (AC)  
MIN  
MAX  
UNIT  
NOTE  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.  
Input Differential Voltage, CK and CK inputs  
Input Crossing Point Voltage, CK and CK inputs  
VREF + 0.35  
VREF - 0.31  
VDDQ+0.6  
V
V
V
0.7  
1
2
0.5*VDDQ-0.2  
0.5*VDDQ+0.2  
Notes:  
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.  
The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same  
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-tion.  
the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.  
URL : www.hbe.co.kr  
6
HANBit Electronics Co.,Ltd.  
REV 1.0 (January. 2005)