欢迎访问ic37.com |
会员登录 免费注册
发布采购

HDD128M72D18RPW-16B 参数 Datasheet PDF下载

HDD128M72D18RPW-16B图片预览
型号: HDD128M72D18RPW-16B
PDF下载: 下载PDF文件 查看货源
内容描述: DDR SDRAM模块1024MByte。点击( 128Mx72bit )的基础上, 64Mx8 , 4Banks , 8K参考, 184PIN -DIMM与PLL和注册 [DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 14 页 / 446 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
 浏览型号HDD128M72D18RPW-16B的Datasheet PDF文件第6页浏览型号HDD128M72D18RPW-16B的Datasheet PDF文件第7页浏览型号HDD128M72D18RPW-16B的Datasheet PDF文件第8页浏览型号HDD128M72D18RPW-16B的Datasheet PDF文件第9页浏览型号HDD128M72D18RPW-16B的Datasheet PDF文件第10页浏览型号HDD128M72D18RPW-16B的Datasheet PDF文件第12页浏览型号HDD128M72D18RPW-16B的Datasheet PDF文件第13页浏览型号HDD128M72D18RPW-16B的Datasheet PDF文件第14页  
HANBit  
HDD128M72D18RPW  
System Notes :  
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.  
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.  
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)  
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)  
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and  
only one output switching.  
Example : For typical slew rate, DQ0 is switching  
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.  
The remaining DQ bits remain the same as for previous state.  
d. Evaluation conditions  
Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process  
Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process  
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process  
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire  
temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown  
drivers due to process variation.  
f. Verified under typical conditions for qualification purposes.  
g. TSOPII package divices only.  
h. Only intended for operation up to 266 Mbps per pin.  
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns  
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or  
VIH(DC) to VIL(DC), similarly for rising transitions.  
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables  
3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the  
lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.  
The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}  
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table  
given, this would result in the need for an increase in tDS and tDH of 100 ps.  
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the  
lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew  
rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.  
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal  
transitions through the DC region must be monotony.  
URL : www.hbe.co.kr  
11  
HANBit Electronics Co.,Ltd.  
REV 1.0 (January. 2005)