HANBit
HDD128M72D18RPW
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CK and /CK are differential clock inputs. All address and control input signals are sampled
on the positive edge of CK and negative edge of /CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/ /CK.
CK, /CK
Clock
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in
any bank). CKE is synchronous for all functions except for disabling outputs, which is
achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during
power-down and self refresh modes, providing low standby power. CKE will recognizean
LVCMOS LOW level prior to VREF being stable on power-up.
CKE
Clock Enable
CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code.
Row/column addresses are multiplexed on the same pins.
/CS0, /CS1
Chip Select
A0 ~ A12
BA0 ~ BA1
/RAS
Address
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command
is being applied.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row
access & precharge.
Latches column addresses on the positive going edge of the CLK with /CAS low. Enables
column access.
/CAS
Enables write operation and row precharge.
/WE
Latches data in starting from /CAS, /WE active.
Output with read data, input with write data. Edge-aligned with read data, cen-tered in write
data. Used to capture write data.
DQS0 ~ 7
Data Strobe
DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
along with that input data during a WRITE access. DM is sampled on both edges of DQS.
DM pins include dummy loading internally, to matches the DQ and DQS load-ing.
DM0~7
Input Data Mask
DQ0 ~ 63
VDDQ
Data input/output
Supply
Data inputs/outputs are multiplexed on the same pins.
DQ Power Supply : +2.5V ± 0.2V.
VDD
VSS
Supply
Supply
Supply
Power Supply : +2.5V ± 0.2V (device specific).
DQ Ground.
VREF
SSTL_2 reference voltage.
VSPD
Supply
Serial EEPROM Power Supply : 3.3v
VDD identification Flag
VDDID
URL : www.hbe.co.kr
4
HANBit Electronics Co.,Ltd.
REV 1.0 (January. 2005)
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
